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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
39 /* DRAM space - 1, size : 2 GB DRAM */
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <100000000>;
46 clock-output-names = "sysclk";
49 gic: interrupt-controller@6000000 {
50 compatible = "arm,gic-v3";
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
56 #interrupt-cells = <3>;
57 #address-cells = <2>;
58 #size-cells = <2>;
60 interrupt-controller;
61 interrupts = <1 9 0x4>;
63 its: gic-its@6020000 {
64 compatible = "arm,gic-v3-its";
65 msi-controller;
66 reg = <0x0 0x6020000 0 0x20000>;
71 compatible = "fsl,ls2080a-rstcr", "syscon";
72 reg = <0x0 0x1e60000 0x0 0x4>;
76 compatible ="syscon-reboot";
78 offset = <0x0>;
79 mask = <0x2>;
82 thermal-zones {
83 ddr-controller1 {
84 polling-delay-passive = <1000>;
85 polling-delay = <5000>;
86 thermal-sensors = <&tmu 1>;
89 ddr-ctrler1-crit {
97 ddr-controller2 {
98 polling-delay-passive = <1000>;
99 polling-delay = <5000>;
100 thermal-sensors = <&tmu 2>;
103 ddr-ctrler2-crit {
111 ddr-controller3 {
112 polling-delay-passive = <1000>;
113 polling-delay = <5000>;
114 thermal-sensors = <&tmu 3>;
117 ddr-ctrler3-crit {
125 core-cluster1 {
126 polling-delay-passive = <1000>;
127 polling-delay = <5000>;
128 thermal-sensors = <&tmu 4>;
131 core_cluster1_alert: core-cluster1-alert {
137 core-cluster1-crit {
144 cooling-maps {
147 cooling-device =
154 core-cluster2 {
155 polling-delay-passive = <1000>;
156 polling-delay = <5000>;
157 thermal-sensors = <&tmu 5>;
160 core_cluster2_alert: core-cluster2-alert {
166 core-cluster2-crit {
173 cooling-maps {
176 cooling-device =
183 core-cluster3 {
184 polling-delay-passive = <1000>;
185 polling-delay = <5000>;
186 thermal-sensors = <&tmu 6>;
189 core_cluster3_alert: core-cluster3-alert {
195 core-cluster3-crit {
202 cooling-maps {
205 cooling-device =
212 core-cluster4 {
213 polling-delay-passive = <1000>;
214 polling-delay = <5000>;
215 thermal-sensors = <&tmu 7>;
218 core_cluster4_alert: core-cluster4-alert {
224 core-cluster4-crit {
231 cooling-maps {
234 cooling-device =
243 compatible = "arm,armv8-timer";
244 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
245 <1 14 4>, /* Physical Non-Secure PPI, active-low */
246 <1 11 4>, /* Virtual PPI, active-low */
247 <1 10 4>; /* Hypervisor PPI, active-low */
248 fsl,erratum-a008585;
252 compatible = "arm,armv8-pmuv3";
253 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
257 compatible = "arm,psci-0.2";
262 compatible = "simple-bus";
263 #address-cells = <2>;
264 #size-cells = <2>;
266 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
269 compatible = "fsl,ls2080a-clockgen";
270 reg = <0 0x1300000 0 0xa0000>;
271 #clock-cells = <2>;
276 compatible = "fsl,ls2080a-dcfg", "syscon";
277 reg = <0x0 0x1e00000 0x0 0x10000>;
278 little-endian;
282 compatible = "fsl,ls2080a-isc", "syscon";
283 reg = <0x0 0x1f70000 0x0 0x10000>;
284 little-endian;
285 #address-cells = <1>;
286 #size-cells = <1>;
287 ranges = <0x0 0x0 0x1f70000 0x10000>;
289 extirq: interrupt-controller@14 {
290 compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
291 #interrupt-cells = <2>;
292 #address-cells = <0>;
293 interrupt-controller;
294 reg = <0x14 4>;
295 interrupt-map =
296 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
297 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
298 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
299 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
300 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
301 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
302 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
303 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
304 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
305 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
306 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
307 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
308 interrupt-map-mask = <0xffffffff 0x0>;
313 compatible = "fsl,qoriq-tmu";
314 reg = <0x0 0x1f80000 0x0 0x10000>;
315 interrupts = <0 23 0x4>;
316 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
317 fsl,tmu-calibration = <0x00000000 0x00000026
318 0x00000001 0x0000002d
319 0x00000002 0x00000032
320 0x00000003 0x00000039
321 0x00000004 0x0000003f
322 0x00000005 0x00000046
323 0x00000006 0x0000004d
324 0x00000007 0x00000054
325 0x00000008 0x0000005a
326 0x00000009 0x00000061
327 0x0000000a 0x0000006a
328 0x0000000b 0x00000071
330 0x00010000 0x00000025
331 0x00010001 0x0000002c
332 0x00010002 0x00000035
333 0x00010003 0x0000003d
334 0x00010004 0x00000045
335 0x00010005 0x0000004e
336 0x00010006 0x00000057
337 0x00010007 0x00000061
338 0x00010008 0x0000006b
339 0x00010009 0x00000076
341 0x00020000 0x00000029
342 0x00020001 0x00000033
343 0x00020002 0x0000003d
344 0x00020003 0x00000049
345 0x00020004 0x00000056
346 0x00020005 0x00000061
347 0x00020006 0x0000006d
349 0x00030000 0x00000021
350 0x00030001 0x0000002a
351 0x00030002 0x0000003c
352 0x00030003 0x0000004e>;
353 little-endian;
354 #thermal-sensor-cells = <1>;
359 reg = <0x0 0x21c0500 0x0 0x100>;
361 QORIQ_CLK_PLL_DIV(4)>;
362 interrupts = <0 32 0x4>; /* Level high type */
367 reg = <0x0 0x21c0600 0x0 0x100>;
369 QORIQ_CLK_PLL_DIV(4)>;
370 interrupts = <0 32 0x4>; /* Level high type */
375 reg = <0x0 0x21d0500 0x0 0x100>;
377 QORIQ_CLK_PLL_DIV(4)>;
378 interrupts = <0 33 0x4>; /* Level high type */
383 reg = <0x0 0x21d0600 0x0 0x100>;
385 QORIQ_CLK_PLL_DIV(4)>;
386 interrupts = <0 33 0x4>; /* Level high type */
390 compatible = "arm,sp805-wdt", "arm,primecell";
391 reg = <0x0 0xc000000 0x0 0x1000>;
393 QORIQ_CLK_PLL_DIV(4)>,
395 QORIQ_CLK_PLL_DIV(4)>;
396 clock-names = "wdog_clk", "apb_pclk";
400 compatible = "arm,sp805-wdt", "arm,primecell";
401 reg = <0x0 0xc010000 0x0 0x1000>;
403 QORIQ_CLK_PLL_DIV(4)>,
405 QORIQ_CLK_PLL_DIV(4)>;
406 clock-names = "wdog_clk", "apb_pclk";
410 compatible = "arm,sp805-wdt", "arm,primecell";
411 reg = <0x0 0xc100000 0x0 0x1000>;
413 QORIQ_CLK_PLL_DIV(4)>,
415 QORIQ_CLK_PLL_DIV(4)>;
416 clock-names = "wdog_clk", "apb_pclk";
420 compatible = "arm,sp805-wdt", "arm,primecell";
421 reg = <0x0 0xc110000 0x0 0x1000>;
423 QORIQ_CLK_PLL_DIV(4)>,
425 QORIQ_CLK_PLL_DIV(4)>;
426 clock-names = "wdog_clk", "apb_pclk";
430 compatible = "arm,sp805-wdt", "arm,primecell";
431 reg = <0x0 0xc200000 0x0 0x1000>;
433 QORIQ_CLK_PLL_DIV(4)>,
435 QORIQ_CLK_PLL_DIV(4)>;
436 clock-names = "wdog_clk", "apb_pclk";
440 compatible = "arm,sp805-wdt", "arm,primecell";
441 reg = <0x0 0xc210000 0x0 0x1000>;
443 QORIQ_CLK_PLL_DIV(4)>,
445 QORIQ_CLK_PLL_DIV(4)>;
446 clock-names = "wdog_clk", "apb_pclk";
450 compatible = "arm,sp805-wdt", "arm,primecell";
451 reg = <0x0 0xc300000 0x0 0x1000>;
453 QORIQ_CLK_PLL_DIV(4)>,
455 QORIQ_CLK_PLL_DIV(4)>;
456 clock-names = "wdog_clk", "apb_pclk";
460 compatible = "arm,sp805-wdt", "arm,primecell";
461 reg = <0x0 0xc310000 0x0 0x1000>;
463 QORIQ_CLK_PLL_DIV(4)>,
465 QORIQ_CLK_PLL_DIV(4)>;
466 clock-names = "wdog_clk", "apb_pclk";
470 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
471 fsl,sec-era = <8>;
472 #address-cells = <1>;
473 #size-cells = <1>;
474 ranges = <0x0 0x00 0x8000000 0x100000>;
475 reg = <0x00 0x8000000 0x0 0x100000>;
477 dma-coherent;
480 compatible = "fsl,sec-v5.0-job-ring",
481 "fsl,sec-v4.0-job-ring";
482 reg = <0x10000 0x10000>;
487 compatible = "fsl,sec-v5.0-job-ring",
488 "fsl,sec-v4.0-job-ring";
489 reg = <0x20000 0x10000>;
494 compatible = "fsl,sec-v5.0-job-ring",
495 "fsl,sec-v4.0-job-ring";
496 reg = <0x30000 0x10000>;
501 compatible = "fsl,sec-v5.0-job-ring",
502 "fsl,sec-v4.0-job-ring";
503 reg = <0x40000 0x10000>;
509 compatible = "fsl,dpaa2-console";
510 reg = <0x00000000 0x08340020 0 0x2>;
513 ptp-timer@8b95000 {
514 compatible = "fsl,dpaa2-ptp";
515 reg = <0x0 0x8b95000 0x0 0x100>;
518 little-endian;
519 fsl,extts-fifo;
523 compatible = "fsl,fman-memac-mdio";
524 reg = <0x0 0x8b96000 0x0 0x1000>;
525 little-endian;
526 #address-cells = <1>;
527 #size-cells = <0>;
532 compatible = "fsl,fman-memac-mdio";
533 reg = <0x0 0x8b97000 0x0 0x1000>;
534 little-endian;
535 #address-cells = <1>;
536 #size-cells = <0>;
541 compatible = "fsl,fman-memac-mdio";
542 reg = <0x0 0x8c07000 0x0 0x1000>;
543 little-endian;
544 #address-cells = <1>;
545 #size-cells = <0>;
548 pcs1: ethernet-phy@0 {
549 reg = <0>;
554 compatible = "fsl,fman-memac-mdio";
555 reg = <0x0 0x8c0b000 0x0 0x1000>;
556 little-endian;
557 #address-cells = <1>;
558 #size-cells = <0>;
561 pcs2: ethernet-phy@0 {
562 reg = <0>;
567 compatible = "fsl,fman-memac-mdio";
568 reg = <0x0 0x8c0f000 0x0 0x1000>;
569 little-endian;
570 #address-cells = <1>;
571 #size-cells = <0>;
574 pcs3: ethernet-phy@0 {
575 reg = <0>;
580 compatible = "fsl,fman-memac-mdio";
581 reg = <0x0 0x8c13000 0x0 0x1000>;
582 little-endian;
583 #address-cells = <1>;
584 #size-cells = <0>;
587 pcs4: ethernet-phy@0 {
588 reg = <0>;
593 compatible = "fsl,fman-memac-mdio";
594 reg = <0x0 0x8c17000 0x0 0x1000>;
595 little-endian;
596 #address-cells = <1>;
597 #size-cells = <0>;
600 pcs5: ethernet-phy@0 {
601 reg = <0>;
606 compatible = "fsl,fman-memac-mdio";
607 reg = <0x0 0x8c1b000 0x0 0x1000>;
608 little-endian;
609 #address-cells = <1>;
610 #size-cells = <0>;
613 pcs6: ethernet-phy@0 {
614 reg = <0>;
619 compatible = "fsl,fman-memac-mdio";
620 reg = <0x0 0x8c1f000 0x0 0x1000>;
621 little-endian;
622 #address-cells = <1>;
623 #size-cells = <0>;
626 pcs7: ethernet-phy@0 {
627 reg = <0>;
632 compatible = "fsl,fman-memac-mdio";
633 reg = <0x0 0x8c23000 0x0 0x1000>;
634 little-endian;
635 #address-cells = <1>;
636 #size-cells = <0>;
639 pcs8: ethernet-phy@0 {
640 reg = <0>;
645 compatible = "fsl,fman-memac-mdio";
646 reg = <0x0 0x8c27000 0x0 0x1000>;
647 little-endian;
648 #address-cells = <1>;
649 #size-cells = <0>;
652 pcs9: ethernet-phy@0 {
653 reg = <0>;
658 compatible = "fsl,fman-memac-mdio";
659 reg = <0x0 0x8c2b000 0x0 0x1000>;
660 little-endian;
661 #address-cells = <1>;
662 #size-cells = <0>;
665 pcs10: ethernet-phy@0 {
666 reg = <0>;
671 compatible = "fsl,fman-memac-mdio";
672 reg = <0x0 0x8c2f000 0x0 0x1000>;
673 little-endian;
674 #address-cells = <1>;
675 #size-cells = <0>;
678 pcs11: ethernet-phy@0 {
679 reg = <0>;
684 compatible = "fsl,fman-memac-mdio";
685 reg = <0x0 0x8c33000 0x0 0x1000>;
686 little-endian;
687 #address-cells = <1>;
688 #size-cells = <0>;
691 pcs12: ethernet-phy@0 {
692 reg = <0>;
697 compatible = "fsl,fman-memac-mdio";
698 reg = <0x0 0x8c37000 0x0 0x1000>;
699 little-endian;
700 #address-cells = <1>;
701 #size-cells = <0>;
704 pcs13: ethernet-phy@0 {
705 reg = <0>;
710 compatible = "fsl,fman-memac-mdio";
711 reg = <0x0 0x8c3b000 0x0 0x1000>;
712 little-endian;
713 #address-cells = <1>;
714 #size-cells = <0>;
717 pcs14: ethernet-phy@0 {
718 reg = <0>;
723 compatible = "fsl,fman-memac-mdio";
724 reg = <0x0 0x8c3f000 0x0 0x1000>;
725 little-endian;
726 #address-cells = <1>;
727 #size-cells = <0>;
730 pcs15: ethernet-phy@0 {
731 reg = <0>;
736 compatible = "fsl,fman-memac-mdio";
737 reg = <0x0 0x8c43000 0x0 0x1000>;
738 little-endian;
739 #address-cells = <1>;
740 #size-cells = <0>;
743 pcs16: ethernet-phy@0 {
744 reg = <0>;
748 fsl_mc: fsl-mc@80c000000 {
749 compatible = "fsl,qoriq-mc";
750 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
751 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
752 msi-parent = <&its>;
753 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
754 dma-coherent;
755 #address-cells = <3>;
756 #size-cells = <1>;
759 * Region type 0x0 - MC portals
760 * Region type 0x1 - QBMAN portals
762 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
763 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
769 #address-cells = <1>;
770 #size-cells = <0>;
773 compatible = "fsl,qoriq-mc-dpmac";
774 reg = <0x1>;
775 pcs-handle = <&pcs1>;
779 compatible = "fsl,qoriq-mc-dpmac";
780 reg = <0x2>;
781 pcs-handle = <&pcs2>;
785 compatible = "fsl,qoriq-mc-dpmac";
786 reg = <0x3>;
787 pcs-handle = <&pcs3>;
790 dpmac4: ethernet@4 {
791 compatible = "fsl,qoriq-mc-dpmac";
792 reg = <0x4>;
793 pcs-handle = <&pcs4>;
797 compatible = "fsl,qoriq-mc-dpmac";
798 reg = <0x5>;
799 pcs-handle = <&pcs5>;
803 compatible = "fsl,qoriq-mc-dpmac";
804 reg = <0x6>;
805 pcs-handle = <&pcs6>;
809 compatible = "fsl,qoriq-mc-dpmac";
810 reg = <0x7>;
811 pcs-handle = <&pcs7>;
815 compatible = "fsl,qoriq-mc-dpmac";
816 reg = <0x8>;
817 pcs-handle = <&pcs8>;
821 compatible = "fsl,qoriq-mc-dpmac";
822 reg = <0x9>;
823 pcs-handle = <&pcs9>;
827 compatible = "fsl,qoriq-mc-dpmac";
828 reg = <0xa>;
829 pcs-handle = <&pcs10>;
833 compatible = "fsl,qoriq-mc-dpmac";
834 reg = <0xb>;
835 pcs-handle = <&pcs11>;
839 compatible = "fsl,qoriq-mc-dpmac";
840 reg = <0xc>;
841 pcs-handle = <&pcs12>;
845 compatible = "fsl,qoriq-mc-dpmac";
846 reg = <0xd>;
847 pcs-handle = <&pcs13>;
851 compatible = "fsl,qoriq-mc-dpmac";
852 reg = <0xe>;
853 pcs-handle = <&pcs14>;
857 compatible = "fsl,qoriq-mc-dpmac";
858 reg = <0xf>;
859 pcs-handle = <&pcs15>;
863 compatible = "fsl,qoriq-mc-dpmac";
864 reg = <0x10>;
865 pcs-handle = <&pcs16>;
871 compatible = "arm,mmu-500";
872 reg = <0 0x5000000 0 0x800000>;
873 #global-interrupts = <12>;
874 #iommu-cells = <1>;
875 stream-match-mask = <0x7C00>;
876 dma-coherent;
877 interrupts = <0 13 4>, /* global secure fault */
878 <0 14 4>, /* combined secure interrupt */
879 <0 15 4>, /* global non-secure fault */
880 <0 16 4>, /* combined non-secure interrupt */
881 /* performance counter interrupts 0-7 */
882 <0 211 4>, <0 212 4>,
883 <0 213 4>, <0 214 4>,
884 <0 215 4>, <0 216 4>,
885 <0 217 4>, <0 218 4>,
887 <0 146 4>, <0 147 4>,
888 <0 148 4>, <0 149 4>,
889 <0 150 4>, <0 151 4>,
890 <0 152 4>, <0 153 4>,
891 <0 154 4>, <0 155 4>,
892 <0 156 4>, <0 157 4>,
893 <0 158 4>, <0 159 4>,
894 <0 160 4>, <0 161 4>,
895 <0 162 4>, <0 163 4>,
896 <0 164 4>, <0 165 4>,
897 <0 166 4>, <0 167 4>,
898 <0 168 4>, <0 169 4>,
899 <0 170 4>, <0 171 4>,
900 <0 172 4>, <0 173 4>,
901 <0 174 4>, <0 175 4>,
902 <0 176 4>, <0 177 4>,
903 <0 178 4>, <0 179 4>,
904 <0 180 4>, <0 181 4>,
905 <0 182 4>, <0 183 4>,
906 <0 184 4>, <0 185 4>,
907 <0 186 4>, <0 187 4>,
908 <0 188 4>, <0 189 4>,
909 <0 190 4>, <0 191 4>,
910 <0 192 4>, <0 193 4>,
911 <0 194 4>, <0 195 4>,
912 <0 196 4>, <0 197 4>,
913 <0 198 4>, <0 199 4>,
914 <0 200 4>, <0 201 4>,
915 <0 202 4>, <0 203 4>,
916 <0 204 4>, <0 205 4>,
917 <0 206 4>, <0 207 4>,
918 <0 208 4>, <0 209 4>;
923 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
924 #address-cells = <1>;
925 #size-cells = <0>;
926 reg = <0x0 0x2100000 0x0 0x10000>;
927 interrupts = <0 26 0x4>; /* Level high type */
929 QORIQ_CLK_PLL_DIV(4)>;
930 clock-names = "dspi";
931 spi-num-chipselects = <5>;
936 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
937 reg = <0x0 0x2140000 0x0 0x10000>;
938 interrupts = <0 28 0x4>; /* Level high type */
941 voltage-ranges = <1800 1800 3300 3300>;
942 sdhci,auto-cmd12;
943 little-endian;
944 bus-width = <4>;
948 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
949 reg = <0x0 0x2300000 0x0 0x10000>;
950 interrupts = <0 36 0x4>; /* Level high type */
951 gpio-controller;
952 little-endian;
953 #gpio-cells = <2>;
954 interrupt-controller;
955 #interrupt-cells = <2>;
959 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
960 reg = <0x0 0x2310000 0x0 0x10000>;
961 interrupts = <0 36 0x4>; /* Level high type */
962 gpio-controller;
963 little-endian;
964 #gpio-cells = <2>;
965 interrupt-controller;
966 #interrupt-cells = <2>;
970 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
971 reg = <0x0 0x2320000 0x0 0x10000>;
972 interrupts = <0 37 0x4>; /* Level high type */
973 gpio-controller;
974 little-endian;
975 #gpio-cells = <2>;
976 interrupt-controller;
977 #interrupt-cells = <2>;
981 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
982 reg = <0x0 0x2330000 0x0 0x10000>;
983 interrupts = <0 37 0x4>; /* Level high type */
984 gpio-controller;
985 little-endian;
986 #gpio-cells = <2>;
987 interrupt-controller;
988 #interrupt-cells = <2>;
993 compatible = "fsl,vf610-i2c";
994 #address-cells = <1>;
995 #size-cells = <0>;
996 reg = <0x0 0x2000000 0x0 0x10000>;
997 interrupts = <0 34 0x4>; /* Level high type */
998 clock-names = "i2c";
1000 QORIQ_CLK_PLL_DIV(4)>;
1005 compatible = "fsl,vf610-i2c";
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008 reg = <0x0 0x2010000 0x0 0x10000>;
1009 interrupts = <0 34 0x4>; /* Level high type */
1010 clock-names = "i2c";
1012 QORIQ_CLK_PLL_DIV(4)>;
1017 compatible = "fsl,vf610-i2c";
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 reg = <0x0 0x2020000 0x0 0x10000>;
1021 interrupts = <0 35 0x4>; /* Level high type */
1022 clock-names = "i2c";
1024 QORIQ_CLK_PLL_DIV(4)>;
1029 compatible = "fsl,vf610-i2c";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 reg = <0x0 0x2030000 0x0 0x10000>;
1033 interrupts = <0 35 0x4>; /* Level high type */
1034 clock-names = "i2c";
1036 QORIQ_CLK_PLL_DIV(4)>;
1040 compatible = "fsl,ifc", "simple-bus";
1041 reg = <0x0 0x2240000 0x0 0x20000>;
1042 interrupts = <0 21 0x4>; /* Level high type */
1043 little-endian;
1044 #address-cells = <2>;
1045 #size-cells = <1>;
1047 ranges = <0 0 0x5 0x80000000 0x08000000
1048 2 0 0x5 0x30000000 0x00010000
1049 3 0 0x5 0x20000000 0x00010000>;
1053 compatible = "fsl,ls2080a-qspi";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 reg = <0x0 0x20c0000 0x0 0x10000>,
1057 <0x0 0x20000000 0x0 0x10000000>;
1058 reg-names = "QuadSPI", "QuadSPI-memory";
1061 QORIQ_CLK_PLL_DIV(4)>,
1063 QORIQ_CLK_PLL_DIV(4)>;
1064 clock-names = "qspi_en", "qspi";
1069 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1070 reg-names = "regs", "config";
1071 interrupts = <0 108 0x4>; /* Level high type */
1072 interrupt-names = "intr";
1073 #address-cells = <3>;
1074 #size-cells = <2>;
1076 dma-coherent;
1077 num-viewport = <6>;
1078 bus-range = <0x0 0xff>;
1079 msi-parent = <&its>;
1080 #interrupt-cells = <1>;
1081 interrupt-map-mask = <0 0 0 7>;
1082 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1083 <0000 0 0 2 &gic 0 0 0 110 4>,
1084 <0000 0 0 3 &gic 0 0 0 111 4>,
1085 <0000 0 0 4 &gic 0 0 0 112 4>;
1086 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1091 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1092 reg-names = "regs", "config";
1093 interrupts = <0 113 0x4>; /* Level high type */
1094 interrupt-names = "intr";
1095 #address-cells = <3>;
1096 #size-cells = <2>;
1098 dma-coherent;
1099 num-viewport = <6>;
1100 bus-range = <0x0 0xff>;
1101 msi-parent = <&its>;
1102 #interrupt-cells = <1>;
1103 interrupt-map-mask = <0 0 0 7>;
1104 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1105 <0000 0 0 2 &gic 0 0 0 115 4>,
1106 <0000 0 0 3 &gic 0 0 0 116 4>,
1107 <0000 0 0 4 &gic 0 0 0 117 4>;
1108 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1113 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1114 reg-names = "regs", "config";
1115 interrupts = <0 118 0x4>; /* Level high type */
1116 interrupt-names = "intr";
1117 #address-cells = <3>;
1118 #size-cells = <2>;
1120 dma-coherent;
1121 num-viewport = <256>;
1122 bus-range = <0x0 0xff>;
1123 msi-parent = <&its>;
1124 #interrupt-cells = <1>;
1125 interrupt-map-mask = <0 0 0 7>;
1126 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1127 <0000 0 0 2 &gic 0 0 0 120 4>,
1128 <0000 0 0 3 &gic 0 0 0 121 4>,
1129 <0000 0 0 4 &gic 0 0 0 122 4>;
1130 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1135 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1136 reg-names = "regs", "config";
1137 interrupts = <0 123 0x4>; /* Level high type */
1138 interrupt-names = "intr";
1139 #address-cells = <3>;
1140 #size-cells = <2>;
1142 dma-coherent;
1143 num-viewport = <6>;
1144 bus-range = <0x0 0xff>;
1145 msi-parent = <&its>;
1146 #interrupt-cells = <1>;
1147 interrupt-map-mask = <0 0 0 7>;
1148 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1149 <0000 0 0 2 &gic 0 0 0 125 4>,
1150 <0000 0 0 3 &gic 0 0 0 126 4>,
1151 <0000 0 0 4 &gic 0 0 0 127 4>;
1152 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1158 compatible = "fsl,ls2080a-ahci";
1159 reg = <0x0 0x3200000 0x0 0x10000>;
1160 interrupts = <0 133 0x4>; /* Level high type */
1162 QORIQ_CLK_PLL_DIV(4)>;
1163 dma-coherent;
1168 compatible = "fsl,ls2080a-ahci";
1169 reg = <0x0 0x3210000 0x0 0x10000>;
1170 interrupts = <0 136 0x4>; /* Level high type */
1172 QORIQ_CLK_PLL_DIV(4)>;
1173 dma-coherent;
1179 reg = <0x0 0x3100000 0x0 0x10000>;
1180 interrupts = <0 80 0x4>; /* Level high type */
1182 snps,quirk-frame-length-adjustment = <0x20>;
1184 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1190 reg = <0x0 0x3110000 0x0 0x10000>;
1191 interrupts = <0 81 0x4>; /* Level high type */
1193 snps,quirk-frame-length-adjustment = <0x20>;
1195 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1199 compatible = "arm,ccn-504";
1200 reg = <0x0 0x04000000 0x0 0x01000000>;
1201 interrupts = <0 12 4>;
1204 rcpm: power-controller@1e34040 {
1205 compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1206 reg = <0x0 0x1e34040 0x0 0x18>;
1207 #fsl,rcpm-wakeup-cells = <6>;
1208 little-endian;
1212 compatible = "fsl,ls208xa-ftm-alarm";
1213 reg = <0x0 0x2800000 0x0 0x10000>;
1214 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1219 ddr1: memory-controller@1080000 {
1220 compatible = "fsl,qoriq-memory-controller";
1221 reg = <0x0 0x1080000 0x0 0x1000>;
1222 interrupts = <0 17 0x4>;
1223 little-endian;
1226 ddr2: memory-controller@1090000 {
1227 compatible = "fsl,qoriq-memory-controller";
1228 reg = <0x0 0x1090000 0x0 0x1000>;
1229 interrupts = <0 18 0x4>;
1230 little-endian;
1235 compatible = "linaro,optee-tz";