Lines Matching +full:phy +full:- +full:handle

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4  * Based on fsl-ls1088a-rdb.dts
5  * Copyright 2017-2020 NXP
6  * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 		stdout-path = "serial0:115200n8";
32 		compatible = "gpio-keys";
55 		compatible = "gpio-leds";
73 	sfp_xg0: dpmac2-sfp {
75 		i2c-bus = <&sfplower_i2c>;
76 		tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
77 		tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
78 		mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
79 		los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
80 		maximum-power-milliwatt = <2000>;
83 	sfp_xg1: dpmac1-sfp {
85 		i2c-bus = <&sfpupper_i2c>;
86 		tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
87 		tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
88 		mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
89 		los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
90 		maximum-power-milliwatt = <2000>;
94 /* XG1 - Upper SFP */
97 	pcs-handle = <&pcs1>;
98 	phy-connection-type = "10gbase-r";
99 	managed = "in-band-status";
102 /* XG0 - Lower SFP */
105 	pcs-handle = <&pcs2>;
106 	phy-connection-type = "10gbase-r";
107 	managed = "in-band-status";
112 	phy-handle = <&mdio1_phy5>;
113 	phy-connection-type = "qsgmii";
114 	managed = "in-band-status";
115 	pcs-handle = <&pcs3_0>;
119 	phy-handle = <&mdio1_phy6>;
120 	phy-connection-type = "qsgmii";
121 	managed = "in-band-status";
122 	pcs-handle = <&pcs3_1>;
126 	phy-handle = <&mdio1_phy7>;
127 	phy-connection-type = "qsgmii";
128 	managed = "in-band-status";
129 	pcs-handle = <&pcs3_2>;
133 	phy-handle = <&mdio1_phy8>;
134 	phy-connection-type = "qsgmii";
135 	managed = "in-band-status";
136 	pcs-handle = <&pcs3_3>;
141 	phy-handle = <&mdio1_phy1>;
142 	phy-connection-type = "qsgmii";
143 	managed = "in-band-status";
144 	pcs-handle = <&pcs7_0>;
148 	phy-handle = <&mdio1_phy2>;
149 	phy-connection-type = "qsgmii";
150 	managed = "in-band-status";
151 	pcs-handle = <&pcs7_1>;
155 	phy-handle = <&mdio1_phy3>;
156 	phy-connection-type = "qsgmii";
157 	managed = "in-band-status";
158 	pcs-handle = <&pcs7_2>;
162 	phy-handle = <&mdio1_phy4>;
163 	phy-connection-type = "qsgmii";
164 	managed = "in-band-status";
165 	pcs-handle = <&pcs7_3>;
179 	mdio1_phy5: ethernet-phy@c {
183 	mdio1_phy6: ethernet-phy@d {
187 	mdio1_phy7: ethernet-phy@e {
191 	mdio1_phy8: ethernet-phy@f {
195 	mdio1_phy1: ethernet-phy@1c {
199 	mdio1_phy2: ethernet-phy@1d {
203 	mdio1_phy3: ethernet-phy@1e {
207 	mdio1_phy4: ethernet-phy@1f {
222 		#gpio-cells = <2>;
223 		gpio-controller;
226 			gpio-hog;
228 			output-low;
250 	i2c-switch@70 {
252 		#address-cells = <1>;
253 		#size-cells = <0>;
257 			#address-cells = <1>;
258 			#size-cells = <0>;
263 			#address-cells = <1>;
264 			#size-cells = <0>;
290 		compatible = "jedec,spi-nor";
291 		#address-cells = <1>;
292 		#size-cells = <1>;
294 		spi-max-frequency = <20000000>;
295 		spi-rx-bus-width = <4>;
296 		spi-tx-bus-width = <4>;
299 			compatible = "fixed-partitions";
300 			#address-cells = <1>;
301 			#size-cells = <1>;
341 		compatible = "spi-nand";
342 		#address-cells = <1>;
343 		#size-cells = <1>;
345 		spi-max-frequency = <20000000>;
346 		spi-rx-bus-width = <4>;
347 		spi-tx-bus-width = <4>;
350 			compatible = "fixed-partitions";
351 			#address-cells = <1>;
352 			#size-cells = <1>;
358 				label = "nand-boot-reserved";
368 			/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */