Lines Matching +full:spi +full:- +full:max +full:- +full:frequency
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
47 compatible = "regulator-fixed";
48 regulator-name = "1P8V";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 regulator-always-on;
54 sb_3v3: regulator-sb3v3 {
55 compatible = "regulator-fixed";
56 regulator-name = "3v3_vbus";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-boot-on;
60 regulator-always-on;
64 compatible = "simple-audio-card";
65 simple-audio-card,format = "i2s";
66 simple-audio-card,widgets =
71 simple-audio-card,routing =
78 simple-audio-card,cpu {
79 sound-dai = <&sai1>;
80 frame-master;
81 bitclock-master;
84 simple-audio-card,codec {
85 sound-dai = <&sgtl5000>;
86 frame-master;
87 bitclock-master;
88 system-clock-frequency = <25000000>;
92 mdio-mux {
93 compatible = "mdio-mux-multiplexer";
94 mux-controls = <&mux 0>;
95 mdio-parent-bus = <&enetc_mdio_pf3>;
96 #address-cells=<1>;
97 #size-cells = <0>;
99 /* on-board RGMII PHY */
101 #address-cells = <1>;
102 #size-cells = <0>;
105 qds_phy1: ethernet-phy@5 {
122 bus-num = <0>;
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "jedec,spi-nor";
129 spi-cpol;
130 spi-cpha;
132 spi-max-frequency = <10000000>;
136 #address-cells = <1>;
137 #size-cells = <1>;
138 compatible = "jedec,spi-nor";
139 spi-cpol;
140 spi-cpha;
142 spi-max-frequency = <10000000>;
146 #address-cells = <1>;
147 #size-cells = <1>;
148 compatible = "jedec,spi-nor";
149 spi-cpol;
150 spi-cpha;
152 spi-max-frequency = <10000000>;
157 bus-num = <1>;
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "jedec,spi-nor";
164 spi-cpol;
165 spi-cpha;
167 spi-max-frequency = <10000000>;
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "jedec,spi-nor";
174 spi-cpol;
175 spi-cpha;
177 spi-max-frequency = <10000000>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 compatible = "jedec,spi-nor";
184 spi-cpol;
185 spi-cpha;
187 spi-max-frequency = <10000000>;
192 bus-num = <2>;
196 #address-cells = <1>;
197 #size-cells = <1>;
198 compatible = "jedec,spi-nor";
199 spi-cpol;
200 spi-cpha;
202 spi-max-frequency = <10000000>;
226 compatible = "jedec,spi-nor";
227 #address-cells = <1>;
228 #size-cells = <1>;
229 spi-max-frequency = <50000000>;
230 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
231 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
232 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
240 i2c-mux@77 {
243 #address-cells = <1>;
244 #size-cells = <0>;
247 #address-cells = <1>;
248 #size-cells = <0>;
251 current-monitor@40 {
254 shunt-resistor = <1000>;
257 current-monitor@41 {
260 shunt-resistor = <1000>;
265 #address-cells = <1>;
266 #size-cells = <0>;
269 temperature-sensor@4c {
272 vcc-supply = <&sb_3v3>;
292 #address-cells = <1>;
293 #size-cells = <0>;
296 sgtl5000: audio-codec@a {
297 #sound-dai-cells = <0>;
300 VDDA-supply = <®_1p8v>;
301 VDDIO-supply = <®_1p8v>;
308 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
309 "simple-mfd";
312 mux: mux-controller {
313 compatible = "reg-mux";
314 #mux-control-cells = <1>;
315 mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
322 phy-handle = <&qds_phy1>;
323 phy-connection-type = "rgmii-id";