Lines Matching +full:s3c6410 +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
43 compatible = "fixed-clock";
44 clock-output-names = "fin_pll";
45 #clock-cells = <0>;
49 #address-cells = <1>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a57";
56 enable-method = "psci";
57 i-cache-size = <0xc000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <256>;
63 next-level-cache = <&atlas_l2>;
68 compatible = "arm,cortex-a57";
70 enable-method = "psci";
71 i-cache-size = <0xc000>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <256>;
74 d-cache-size = <0x8000>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <256>;
77 next-level-cache = <&atlas_l2>;
82 compatible = "arm,cortex-a57";
84 enable-method = "psci";
85 i-cache-size = <0xc000>;
86 i-cache-line-size = <64>;
87 i-cache-sets = <256>;
88 d-cache-size = <0x8000>;
89 d-cache-line-size = <64>;
90 d-cache-sets = <256>;
91 next-level-cache = <&atlas_l2>;
96 compatible = "arm,cortex-a57";
98 enable-method = "psci";
99 i-cache-size = <0xc000>;
100 i-cache-line-size = <64>;
101 i-cache-sets = <256>;
102 d-cache-size = <0x8000>;
103 d-cache-line-size = <64>;
104 d-cache-sets = <256>;
105 next-level-cache = <&atlas_l2>;
108 atlas_l2: l2-cache0 {
110 cache-size = <0x200000>;
111 cache-line-size = <64>;
112 cache-sets = <2048>;
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
130 compatible = "samsung,exynos4210-chipid";
134 gic: interrupt-controller@11001000 {
135 compatible = "arm,gic-400";
136 #interrupt-cells = <3>;
137 #address-cells = <0>;
138 interrupt-controller;
150 clock-names = "apb_pclk";
151 #dma-cells = <1>;
152 #dma-channels = <8>;
153 #dma-requests = <32>;
161 clock-names = "apb_pclk";
162 #dma-cells = <1>;
163 #dma-channels = <8>;
164 #dma-requests = <32>;
167 clock_topc: clock-controller@10570000 {
168 compatible = "samsung,exynos7-clock-topc";
170 #clock-cells = <1>;
173 clock_top0: clock-controller@105d0000 {
174 compatible = "samsung,exynos7-clock-top0";
176 #clock-cells = <1>;
181 clock-names = "fin_pll", "dout_sclk_bus0_pll",
186 clock_top1: clock-controller@105e0000 {
187 compatible = "samsung,exynos7-clock-top1";
189 #clock-cells = <1>;
194 clock-names = "fin_pll", "dout_sclk_bus0_pll",
199 clock_ccore: clock-controller@105b0000 {
200 compatible = "samsung,exynos7-clock-ccore";
202 #clock-cells = <1>;
204 clock-names = "fin_pll", "dout_aclk_ccore_133";
207 clock_peric0: clock-controller@13610000 {
208 compatible = "samsung,exynos7-clock-peric0";
210 #clock-cells = <1>;
213 clock-names = "fin_pll", "dout_aclk_peric0_66",
217 clock_peric1: clock-controller@14c80000 {
218 compatible = "samsung,exynos7-clock-peric1";
220 #clock-cells = <1>;
225 clock-names = "fin_pll", "dout_aclk_peric1_66",
229 clock_peris: clock-controller@10040000 {
230 compatible = "samsung,exynos7-clock-peris";
232 #clock-cells = <1>;
234 clock-names = "fin_pll", "dout_aclk_peris_66";
237 clock_fsys0: clock-controller@10e90000 {
238 compatible = "samsung,exynos7-clock-fsys0";
240 #clock-cells = <1>;
243 clock-names = "fin_pll", "dout_aclk_fsys0_200",
247 clock_fsys1: clock-controller@156e0000 {
248 compatible = "samsung,exynos7-clock-fsys1";
250 #clock-cells = <1>;
257 clock-names = "fin_pll", "dout_aclk_fsys1_200",
264 compatible = "samsung,exynos4210-uart";
269 clock-names = "uart", "clk_uart_baud0";
274 compatible = "samsung,exynos4210-uart";
279 clock-names = "uart", "clk_uart_baud0";
284 compatible = "samsung,exynos4210-uart";
289 clock-names = "uart", "clk_uart_baud0";
294 compatible = "samsung,exynos4210-uart";
299 clock-names = "uart", "clk_uart_baud0";
304 compatible = "samsung,exynos7-pinctrl";
307 wakeup-interrupt-controller {
308 compatible = "samsung,exynos7-wakeup-eint";
309 interrupt-parent = <&gic>;
315 compatible = "samsung,exynos7-pinctrl";
321 compatible = "samsung,exynos7-pinctrl";
327 compatible = "samsung,exynos7-pinctrl";
333 compatible = "samsung,exynos7-pinctrl";
339 compatible = "samsung,exynos7-pinctrl";
345 compatible = "samsung,exynos7-pinctrl";
351 compatible = "samsung,exynos7-pinctrl";
357 compatible = "samsung,exynos7-pinctrl";
363 compatible = "samsung,exynos7-hsi2c";
366 #address-cells = <1>;
367 #size-cells = <0>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&hs_i2c0_bus>;
371 clock-names = "hsi2c";
376 compatible = "samsung,exynos7-hsi2c";
379 #address-cells = <1>;
380 #size-cells = <0>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&hs_i2c1_bus>;
384 clock-names = "hsi2c";
389 compatible = "samsung,exynos7-hsi2c";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&hs_i2c2_bus>;
397 clock-names = "hsi2c";
402 compatible = "samsung,exynos7-hsi2c";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&hs_i2c3_bus>;
410 clock-names = "hsi2c";
415 compatible = "samsung,exynos7-hsi2c";
418 #address-cells = <1>;
419 #size-cells = <0>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&hs_i2c4_bus>;
423 clock-names = "hsi2c";
428 compatible = "samsung,exynos7-hsi2c";
431 #address-cells = <1>;
432 #size-cells = <0>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&hs_i2c5_bus>;
436 clock-names = "hsi2c";
441 compatible = "samsung,exynos7-hsi2c";
444 #address-cells = <1>;
445 #size-cells = <0>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&hs_i2c6_bus>;
449 clock-names = "hsi2c";
454 compatible = "samsung,exynos7-hsi2c";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&hs_i2c7_bus>;
462 clock-names = "hsi2c";
467 compatible = "samsung,exynos7-hsi2c";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 pinctrl-names = "default";
473 pinctrl-0 = <&hs_i2c8_bus>;
475 clock-names = "hsi2c";
480 compatible = "samsung,exynos7-hsi2c";
483 #address-cells = <1>;
484 #size-cells = <0>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&hs_i2c9_bus>;
488 clock-names = "hsi2c";
493 compatible = "samsung,exynos7-hsi2c";
496 #address-cells = <1>;
497 #size-cells = <0>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&hs_i2c10_bus>;
501 clock-names = "hsi2c";
506 compatible = "samsung,exynos7-hsi2c";
509 #address-cells = <1>;
510 #size-cells = <0>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&hs_i2c11_bus>;
514 clock-names = "hsi2c";
518 pmu_system_controller: system-controller@105c0000 {
519 compatible = "samsung,exynos7-pmu", "syscon";
523 rtc: rtc@10590000 { label
524 compatible = "samsung,s3c6410-rtc";
529 clock-names = "rtc";
534 compatible = "samsung,exynos7-wdt";
538 clock-names = "watchdog";
539 samsung,syscon-phandle = <&pmu_system_controller>;
544 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
549 interrupt-names = "job", "mmu", "gpu";
555 compatible = "samsung,exynos7-dw-mshc-smu";
557 #address-cells = <1>;
558 #size-cells = <0>;
562 clock-names = "biu", "ciu";
563 fifo-depth = <0x40>;
568 compatible = "samsung,exynos7-dw-mshc";
570 #address-cells = <1>;
571 #size-cells = <0>;
575 clock-names = "biu", "ciu";
576 fifo-depth = <0x40>;
581 compatible = "samsung,exynos7-dw-mshc-smu";
583 #address-cells = <1>;
584 #size-cells = <0>;
588 clock-names = "biu", "ciu";
589 fifo-depth = <0x40>;
594 compatible = "samsung,exynos7-adc";
598 clock-names = "adc";
599 #io-channel-cells = <1>;
604 compatible = "samsung,exynos4210-pwm";
611 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
612 #pwm-cells = <3>;
614 clock-names = "timers";
618 compatible = "samsung,exynos7-tmu";
623 clock-names = "tmu_apbif", "tmu_sclk";
624 #thermal-sensor-cells = <0>;
628 compatible = "samsung,exynos7-ufs";
633 reg-names = "hci", "vs_hci", "unipro", "ufsp";
637 clock-names = "core_clk", "sclk_unipro_main";
638 freq-table-hz = <0 0>, <0 0>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
642 phy-names = "ufs-phy";
646 ufs_phy: ufs-phy@15571800 {
647 compatible = "samsung,exynos7-ufs-phy";
649 reg-names = "phy-pma";
650 samsung,pmu-syscon = <&pmu_system_controller>;
651 #phy-cells = <0>;
656 clock-names = "ref_clk", "rx1_symbol_clk",
662 compatible = "samsung,exynos7-usbdrd-phy";
669 clock-names = "phy", "ref", "phy_pipe",
671 samsung,pmu-syscon = <&pmu_system_controller>;
672 #phy-cells = <1>;
676 compatible = "samsung,exynos7-dwusb3";
680 clock-names = "usbdrd30", "usbdrd30_susp_clk",
682 #address-cells = <1>;
683 #size-cells = <1>;
691 phy-names = "usb2-phy", "usb3-phy";
696 thermal-zones {
697 atlas_thermal: cluster0-thermal {
698 polling-delay-passive = <0>; /* milliseconds */
699 polling-delay = <0>; /* milliseconds */
700 thermal-sensors = <&tmuctrl_0>;
701 #include "exynos7-trip-points.dtsi"
706 compatible = "arm,armv8-timer";
718 #include "exynos7-pinctrl.dtsi"
719 #include "arm/exynos-syscon-restart.dtsi"