Lines Matching +full:power +full:- +full:domain +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
36 compatible = "arm,cortex-a57-pmu";
41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
46 compatible = "fixed-clock";
47 clock-output-names = "oscclk";
48 #clock-cells = <0>;
52 #address-cells = <1>;
53 #size-cells = <0>;
55 cpu-map {
89 compatible = "arm,cortex-a53";
90 enable-method = "psci";
92 clock-frequency = <1300000000>;
94 clock-names = "apolloclk";
95 operating-points-v2 = <&cluster_a53_opp_table>;
96 #cooling-cells = <2>;
97 i-cache-size = <0x8000>;
98 i-cache-line-size = <64>;
99 i-cache-sets = <256>;
100 d-cache-size = <0x8000>;
101 d-cache-line-size = <64>;
102 d-cache-sets = <128>;
103 next-level-cache = <&cluster_a53_l2>;
108 compatible = "arm,cortex-a53";
109 enable-method = "psci";
111 clock-frequency = <1300000000>;
112 operating-points-v2 = <&cluster_a53_opp_table>;
113 #cooling-cells = <2>;
114 i-cache-size = <0x8000>;
115 i-cache-line-size = <64>;
116 i-cache-sets = <256>;
117 d-cache-size = <0x8000>;
118 d-cache-line-size = <64>;
119 d-cache-sets = <128>;
120 next-level-cache = <&cluster_a53_l2>;
125 compatible = "arm,cortex-a53";
126 enable-method = "psci";
128 clock-frequency = <1300000000>;
129 operating-points-v2 = <&cluster_a53_opp_table>;
130 #cooling-cells = <2>;
131 i-cache-size = <0x8000>;
132 i-cache-line-size = <64>;
133 i-cache-sets = <256>;
134 d-cache-size = <0x8000>;
135 d-cache-line-size = <64>;
136 d-cache-sets = <128>;
137 next-level-cache = <&cluster_a53_l2>;
142 compatible = "arm,cortex-a53";
143 enable-method = "psci";
145 clock-frequency = <1300000000>;
146 operating-points-v2 = <&cluster_a53_opp_table>;
147 #cooling-cells = <2>;
148 i-cache-size = <0x8000>;
149 i-cache-line-size = <64>;
150 i-cache-sets = <256>;
151 d-cache-size = <0x8000>;
152 d-cache-line-size = <64>;
153 d-cache-sets = <128>;
154 next-level-cache = <&cluster_a53_l2>;
159 compatible = "arm,cortex-a57";
160 enable-method = "psci";
162 clock-frequency = <1900000000>;
164 clock-names = "atlasclk";
165 operating-points-v2 = <&cluster_a57_opp_table>;
166 #cooling-cells = <2>;
167 i-cache-size = <0xc000>;
168 i-cache-line-size = <64>;
169 i-cache-sets = <256>;
170 d-cache-size = <0x8000>;
171 d-cache-line-size = <64>;
172 d-cache-sets = <256>;
173 next-level-cache = <&cluster_a57_l2>;
178 compatible = "arm,cortex-a57";
179 enable-method = "psci";
181 clock-frequency = <1900000000>;
182 operating-points-v2 = <&cluster_a57_opp_table>;
183 #cooling-cells = <2>;
184 i-cache-size = <0xc000>;
185 i-cache-line-size = <64>;
186 i-cache-sets = <256>;
187 d-cache-size = <0x8000>;
188 d-cache-line-size = <64>;
189 d-cache-sets = <256>;
190 next-level-cache = <&cluster_a57_l2>;
195 compatible = "arm,cortex-a57";
196 enable-method = "psci";
198 clock-frequency = <1900000000>;
199 operating-points-v2 = <&cluster_a57_opp_table>;
200 #cooling-cells = <2>;
201 i-cache-size = <0xc000>;
202 i-cache-line-size = <64>;
203 i-cache-sets = <256>;
204 d-cache-size = <0x8000>;
205 d-cache-line-size = <64>;
206 d-cache-sets = <256>;
207 next-level-cache = <&cluster_a57_l2>;
212 compatible = "arm,cortex-a57";
213 enable-method = "psci";
215 clock-frequency = <1900000000>;
216 operating-points-v2 = <&cluster_a57_opp_table>;
217 #cooling-cells = <2>;
218 i-cache-size = <0xc000>;
219 i-cache-line-size = <64>;
220 i-cache-sets = <256>;
221 d-cache-size = <0x8000>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <256>;
224 next-level-cache = <&cluster_a57_l2>;
227 cluster_a57_l2: l2-cache0 {
229 cache-size = <0x200000>;
230 cache-line-size = <64>;
231 cache-sets = <2048>;
234 cluster_a53_l2: l2-cache1 {
236 cache-size = <0x40000>;
237 cache-line-size = <64>;
238 cache-sets = <256>;
242 cluster_a53_opp_table: opp-table0 {
243 compatible = "operating-points-v2";
244 opp-shared;
246 opp-400000000 {
247 opp-hz = /bits/ 64 <400000000>;
248 opp-microvolt = <900000>;
250 opp-500000000 {
251 opp-hz = /bits/ 64 <500000000>;
252 opp-microvolt = <925000>;
254 opp-600000000 {
255 opp-hz = /bits/ 64 <600000000>;
256 opp-microvolt = <950000>;
258 opp-700000000 {
259 opp-hz = /bits/ 64 <700000000>;
260 opp-microvolt = <975000>;
262 opp-800000000 {
263 opp-hz = /bits/ 64 <800000000>;
264 opp-microvolt = <1000000>;
266 opp-900000000 {
267 opp-hz = /bits/ 64 <900000000>;
268 opp-microvolt = <1050000>;
270 opp-1000000000 {
271 opp-hz = /bits/ 64 <1000000000>;
272 opp-microvolt = <1075000>;
274 opp-1100000000 {
275 opp-hz = /bits/ 64 <1100000000>;
276 opp-microvolt = <1112500>;
278 opp-1200000000 {
279 opp-hz = /bits/ 64 <1200000000>;
280 opp-microvolt = <1112500>;
282 opp-1300000000 {
283 opp-hz = /bits/ 64 <1300000000>;
284 opp-microvolt = <1150000>;
288 cluster_a57_opp_table: opp-table1 {
289 compatible = "operating-points-v2";
290 opp-shared;
292 opp-500000000 {
293 opp-hz = /bits/ 64 <500000000>;
294 opp-microvolt = <900000>;
296 opp-600000000 {
297 opp-hz = /bits/ 64 <600000000>;
298 opp-microvolt = <900000>;
300 opp-700000000 {
301 opp-hz = /bits/ 64 <700000000>;
302 opp-microvolt = <912500>;
304 opp-800000000 {
305 opp-hz = /bits/ 64 <800000000>;
306 opp-microvolt = <912500>;
308 opp-900000000 {
309 opp-hz = /bits/ 64 <900000000>;
310 opp-microvolt = <937500>;
312 opp-1000000000 {
313 opp-hz = /bits/ 64 <1000000000>;
314 opp-microvolt = <975000>;
316 opp-1100000000 {
317 opp-hz = /bits/ 64 <1100000000>;
318 opp-microvolt = <1012500>;
320 opp-1200000000 {
321 opp-hz = /bits/ 64 <1200000000>;
322 opp-microvolt = <1037500>;
324 opp-1300000000 {
325 opp-hz = /bits/ 64 <1300000000>;
326 opp-microvolt = <1062500>;
328 opp-1400000000 {
329 opp-hz = /bits/ 64 <1400000000>;
330 opp-microvolt = <1087500>;
332 opp-1500000000 {
333 opp-hz = /bits/ 64 <1500000000>;
334 opp-microvolt = <1125000>;
336 opp-1600000000 {
337 opp-hz = /bits/ 64 <1600000000>;
338 opp-microvolt = <1137500>;
340 opp-1700000000 {
341 opp-hz = /bits/ 64 <1700000000>;
342 opp-microvolt = <1175000>;
344 opp-1800000000 {
345 opp-hz = /bits/ 64 <1800000000>;
346 opp-microvolt = <1212500>;
348 opp-1900000000 {
349 opp-hz = /bits/ 64 <1900000000>;
350 opp-microvolt = <1262500>;
362 compatible = "simple-bus";
363 #address-cells = <1>;
364 #size-cells = <1>;
368 compatible = "samsung,exynos4210-chipid";
372 cmu_top: clock-controller@10030000 {
373 compatible = "samsung,exynos5433-cmu-top";
375 #clock-cells = <1>;
377 clock-names = "oscclk",
387 cmu_cpif: clock-controller@10fc0000 {
388 compatible = "samsung,exynos5433-cmu-cpif";
390 #clock-cells = <1>;
392 clock-names = "oscclk";
396 cmu_mif: clock-controller@105b0000 {
397 compatible = "samsung,exynos5433-cmu-mif";
399 #clock-cells = <1>;
401 clock-names = "oscclk",
407 cmu_peric: clock-controller@14c80000 {
408 compatible = "samsung,exynos5433-cmu-peric";
410 #clock-cells = <1>;
413 cmu_peris: clock-controller@10040000 {
414 compatible = "samsung,exynos5433-cmu-peris";
416 #clock-cells = <1>;
419 cmu_fsys: clock-controller@156e0000 {
420 compatible = "samsung,exynos5433-cmu-fsys";
422 #clock-cells = <1>;
424 clock-names = "oscclk",
446 cmu_g2d: clock-controller@12460000 {
447 compatible = "samsung,exynos5433-cmu-g2d";
449 #clock-cells = <1>;
451 clock-names = "oscclk",
457 power-domains = <&pd_g2d>;
460 cmu_disp: clock-controller@13b90000 {
461 compatible = "samsung,exynos5433-cmu-disp";
463 #clock-cells = <1>;
465 clock-names = "oscclk",
483 power-domains = <&pd_disp>;
486 cmu_aud: clock-controller@114c0000 {
487 compatible = "samsung,exynos5433-cmu-aud";
489 #clock-cells = <1>;
490 clock-names = "oscclk", "fout_aud_pll";
492 power-domains = <&pd_aud>;
495 cmu_bus0: clock-controller@13600000 {
496 compatible = "samsung,exynos5433-cmu-bus0";
498 #clock-cells = <1>;
500 clock-names = "aclk_bus0_400";
504 cmu_bus1: clock-controller@14800000 {
505 compatible = "samsung,exynos5433-cmu-bus1";
507 #clock-cells = <1>;
509 clock-names = "aclk_bus1_400";
513 cmu_bus2: clock-controller@13400000 {
514 compatible = "samsung,exynos5433-cmu-bus2";
516 #clock-cells = <1>;
518 clock-names = "oscclk", "aclk_bus2_400";
522 cmu_g3d: clock-controller@14aa0000 {
523 compatible = "samsung,exynos5433-cmu-g3d";
525 #clock-cells = <1>;
527 clock-names = "oscclk", "aclk_g3d_400";
529 power-domains = <&pd_g3d>;
532 cmu_gscl: clock-controller@13cf0000 {
533 compatible = "samsung,exynos5433-cmu-gscl";
535 #clock-cells = <1>;
537 clock-names = "oscclk",
543 power-domains = <&pd_gscl>;
546 cmu_apollo: clock-controller@11900000 {
547 compatible = "samsung,exynos5433-cmu-apollo";
549 #clock-cells = <1>;
551 clock-names = "oscclk", "sclk_bus_pll_apollo";
555 cmu_atlas: clock-controller@11800000 {
556 compatible = "samsung,exynos5433-cmu-atlas";
558 #clock-cells = <1>;
560 clock-names = "oscclk", "sclk_bus_pll_atlas";
564 cmu_mscl: clock-controller@150d0000 {
565 compatible = "samsung,exynos5433-cmu-mscl";
567 #clock-cells = <1>;
569 clock-names = "oscclk",
575 power-domains = <&pd_mscl>;
578 cmu_mfc: clock-controller@15280000 {
579 compatible = "samsung,exynos5433-cmu-mfc";
581 #clock-cells = <1>;
583 clock-names = "oscclk", "aclk_mfc_400";
585 power-domains = <&pd_mfc>;
588 cmu_hevc: clock-controller@14f80000 {
589 compatible = "samsung,exynos5433-cmu-hevc";
591 #clock-cells = <1>;
593 clock-names = "oscclk", "aclk_hevc_400";
595 power-domains = <&pd_hevc>;
598 cmu_isp: clock-controller@146d0000 {
599 compatible = "samsung,exynos5433-cmu-isp";
601 #clock-cells = <1>;
603 clock-names = "oscclk",
609 power-domains = <&pd_isp>;
612 cmu_cam0: clock-controller@120d0000 {
613 compatible = "samsung,exynos5433-cmu-cam0";
615 #clock-cells = <1>;
617 clock-names = "oscclk",
625 power-domains = <&pd_cam0>;
628 cmu_cam1: clock-controller@145d0000 {
629 compatible = "samsung,exynos5433-cmu-cam1";
631 #clock-cells = <1>;
633 clock-names = "oscclk",
647 power-domains = <&pd_cam1>;
650 cmu_imem: clock-controller@11060000 {
651 compatible = "samsung,exynos5433-cmu-imem";
653 #clock-cells = <1>;
655 clock-names = "oscclk",
665 slim_sss: slim-sss@11140000 {
666 compatible = "samsung,exynos5433-slim-sss";
669 clock-names = "pclk", "aclk";
674 pd_gscl: power-domain@105c4000 {
675 compatible = "samsung,exynos5433-pd";
677 #power-domain-cells = <0>;
681 pd_cam0: power-domain@105c4020 {
682 compatible = "samsung,exynos5433-pd";
684 #power-domain-cells = <0>;
685 power-domains = <&pd_cam1>;
689 pd_mscl: power-domain@105c4040 {
690 compatible = "samsung,exynos5433-pd";
692 #power-domain-cells = <0>;
696 pd_g3d: power-domain@105c4060 {
697 compatible = "samsung,exynos5433-pd";
699 #power-domain-cells = <0>;
703 pd_disp: power-domain@105c4080 {
704 compatible = "samsung,exynos5433-pd";
706 #power-domain-cells = <0>;
710 pd_cam1: power-domain@105c40a0 {
711 compatible = "samsung,exynos5433-pd";
713 #power-domain-cells = <0>;
717 pd_aud: power-domain@105c40c0 {
718 compatible = "samsung,exynos5433-pd";
720 #power-domain-cells = <0>;
724 pd_g2d: power-domain@105c4120 {
725 compatible = "samsung,exynos5433-pd";
727 #power-domain-cells = <0>;
731 pd_isp: power-domain@105c4140 {
732 compatible = "samsung,exynos5433-pd";
734 #power-domain-cells = <0>;
735 power-domains = <&pd_cam0>;
739 pd_mfc: power-domain@105c4180 {
740 compatible = "samsung,exynos5433-pd";
742 #power-domain-cells = <0>;
746 pd_hevc: power-domain@105c41c0 {
747 compatible = "samsung,exynos5433-pd";
749 #power-domain-cells = <0>;
754 compatible = "samsung,exynos5433-tmu";
759 clock-names = "tmu_apbif", "tmu_sclk";
760 #thermal-sensor-cells = <0>;
765 compatible = "samsung,exynos5433-tmu";
770 clock-names = "tmu_apbif", "tmu_sclk";
771 #thermal-sensor-cells = <0>;
776 compatible = "samsung,exynos5433-tmu";
781 clock-names = "tmu_apbif", "tmu_sclk";
782 #thermal-sensor-cells = <0>;
787 compatible = "samsung,exynos5433-tmu";
792 clock-names = "tmu_apbif", "tmu_sclk";
793 #thermal-sensor-cells = <0>;
798 compatible = "samsung,exynos5433-tmu";
803 clock-names = "tmu_apbif", "tmu_sclk";
804 #thermal-sensor-cells = <0>;
809 compatible = "samsung,exynos4210-mct";
824 clock-names = "fin_pll", "mct";
828 compatible = "samsung,exynos-ppmu-v2";
834 compatible = "samsung,exynos-ppmu-v2";
840 compatible = "samsung,exynos-ppmu-v2";
846 compatible = "samsung,exynos-ppmu-v2";
852 compatible = "samsung,exynos5433-pinctrl";
855 wakeup-interrupt-controller {
856 compatible = "samsung,exynos7-wakeup-eint";
862 compatible = "samsung,exynos5433-pinctrl";
865 power-domains = <&pd_aud>;
869 compatible = "samsung,exynos5433-pinctrl";
875 compatible = "samsung,exynos5433-pinctrl";
881 compatible = "samsung,exynos5433-pinctrl";
887 compatible = "samsung,exynos5433-pinctrl";
893 compatible = "samsung,exynos5433-pinctrl";
899 compatible = "samsung,exynos5433-pinctrl";
905 compatible = "samsung,exynos5433-pinctrl";
911 compatible = "samsung,exynos5433-pinctrl";
916 pmu_system_controller: system-controller@105c0000 {
917 compatible = "samsung,exynos5433-pmu", "syscon";
919 #clock-cells = <1>;
920 clock-names = "clkout16";
923 reboot: syscon-reboot {
924 compatible = "syscon-reboot";
931 gic: interrupt-controller@11001000 {
932 compatible = "arm,gic-400";
933 #interrupt-cells = <3>;
934 interrupt-controller;
942 mipi_phy: video-phy {
943 compatible = "samsung,exynos5433-mipi-video-phy";
944 #phy-cells = <1>;
945 samsung,pmu-syscon = <&pmu_system_controller>;
946 samsung,cam0-sysreg = <&syscon_cam0>;
947 samsung,cam1-sysreg = <&syscon_cam1>;
948 samsung,disp-sysreg = <&syscon_disp>;
952 compatible = "samsung,exynos5433-decon";
965 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
970 power-domains = <&pd_disp>;
971 interrupt-names = "fifo", "vsync", "lcd_sys";
975 samsung,disp-sysreg = <&syscon_disp>;
978 iommu-names = "m0", "m1";
981 #address-cells = <1>;
982 #size-cells = <0>;
987 remote-endpoint =
995 compatible = "samsung,exynos5433-decon-tv";
1008 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
1013 samsung,disp-sysreg = <&syscon_disp>;
1014 power-domains = <&pd_disp>;
1015 interrupt-names = "fifo", "vsync", "lcd_sys";
1021 iommu-names = "m0", "m1";
1025 compatible = "samsung,exynos5433-mipi-dsi";
1029 phy-names = "dsim";
1035 clock-names = "bus_clk",
1040 power-domains = <&pd_disp>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1052 remote-endpoint = <&mic_to_dsi>;
1059 compatible = "samsung,exynos5433-mic";
1063 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1064 power-domains = <&pd_disp>;
1065 samsung,disp-syscon = <&syscon_disp>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1075 remote-endpoint =
1083 remote-endpoint = <&dsi_to_mic>;
1090 compatible = "samsung,exynos5433-hdmi";
1102 clock-names = "hdmi_pclk", "hdmi_i_pclk",
1109 samsung,syscon-phandle = <&pmu_system_controller>;
1110 samsung,sysreg-phandle = <&syscon_disp>;
1111 #sound-dai-cells = <0>;
1120 compatible = "samsung,exynos5433-sysreg", "syscon";
1125 compatible = "samsung,exynos5433-sysreg", "syscon";
1130 compatible = "samsung,exynos5433-sysreg", "syscon";
1139 gsc_0: video-scaler@13c00000 {
1140 compatible = "samsung,exynos5433-gsc";
1143 clock-names = "pclk", "aclk", "aclk_xiu",
1151 power-domains = <&pd_gscl>;
1154 gsc_1: video-scaler@13c10000 {
1155 compatible = "samsung,exynos5433-gsc";
1158 clock-names = "pclk", "aclk", "aclk_xiu",
1166 power-domains = <&pd_gscl>;
1169 gsc_2: video-scaler@13c20000 {
1170 compatible = "samsung,exynos5433-gsc";
1173 clock-names = "pclk", "aclk", "aclk_xiu",
1181 power-domains = <&pd_gscl>;
1185 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1190 interrupt-names = "job", "mmu", "gpu";
1192 clock-names = "core";
1193 power-domains = <&pd_g3d>;
1194 operating-points-v2 = <&gpu_opp_table>;
1197 gpu_opp_table: opp-table {
1198 compatible = "operating-points-v2";
1200 opp-160000000 {
1201 opp-hz = /bits/ 64 <160000000>;
1202 opp-microvolt = <1000000>;
1204 opp-267000000 {
1205 opp-hz = /bits/ 64 <267000000>;
1206 opp-microvolt = <1000000>;
1208 opp-350000000 {
1209 opp-hz = /bits/ 64 <350000000>;
1210 opp-microvolt = <1025000>;
1212 opp-420000000 {
1213 opp-hz = /bits/ 64 <420000000>;
1214 opp-microvolt = <1025000>;
1216 opp-500000000 {
1217 opp-hz = /bits/ 64 <500000000>;
1218 opp-microvolt = <1075000>;
1220 opp-550000000 {
1221 opp-hz = /bits/ 64 <550000000>;
1222 opp-microvolt = <1125000>;
1224 opp-600000000 {
1225 opp-hz = /bits/ 64 <600000000>;
1226 opp-microvolt = <1150000>;
1228 opp-700000000 {
1229 opp-hz = /bits/ 64 <700000000>;
1230 opp-microvolt = <1150000>;
1236 compatible = "samsung,exynos5433-scaler";
1239 clock-names = "pclk", "aclk", "aclk_xiu";
1244 power-domains = <&pd_mscl>;
1248 compatible = "samsung,exynos5433-scaler";
1251 clock-names = "pclk", "aclk", "aclk_xiu";
1256 power-domains = <&pd_mscl>;
1260 compatible = "samsung,exynos5433-jpeg";
1263 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1269 power-domains = <&pd_mscl>;
1273 compatible = "samsung,exynos5433-mfc";
1276 clock-names = "pclk", "aclk", "aclk_xiu";
1281 iommu-names = "left", "right";
1282 power-domains = <&pd_mfc>;
1286 compatible = "samsung,exynos-sysmmu";
1289 clock-names = "aclk", "pclk";
1292 power-domains = <&pd_disp>;
1293 #iommu-cells = <0>;
1297 compatible = "samsung,exynos-sysmmu";
1300 clock-names = "aclk", "pclk";
1303 #iommu-cells = <0>;
1304 power-domains = <&pd_disp>;
1308 compatible = "samsung,exynos-sysmmu";
1311 clock-names = "aclk", "pclk";
1314 #iommu-cells = <0>;
1315 power-domains = <&pd_disp>;
1319 compatible = "samsung,exynos-sysmmu";
1322 clock-names = "aclk", "pclk";
1325 #iommu-cells = <0>;
1326 power-domains = <&pd_disp>;
1330 compatible = "samsung,exynos-sysmmu";
1333 clock-names = "aclk", "pclk";
1336 #iommu-cells = <0>;
1337 power-domains = <&pd_gscl>;
1341 compatible = "samsung,exynos-sysmmu";
1344 clock-names = "aclk", "pclk";
1347 #iommu-cells = <0>;
1348 power-domains = <&pd_gscl>;
1352 compatible = "samsung,exynos-sysmmu";
1355 clock-names = "aclk", "pclk";
1358 #iommu-cells = <0>;
1359 power-domains = <&pd_gscl>;
1363 compatible = "samsung,exynos-sysmmu";
1366 clock-names = "aclk", "pclk";
1369 #iommu-cells = <0>;
1370 power-domains = <&pd_mscl>;
1374 compatible = "samsung,exynos-sysmmu";
1377 clock-names = "aclk", "pclk";
1380 #iommu-cells = <0>;
1381 power-domains = <&pd_mscl>;
1385 compatible = "samsung,exynos-sysmmu";
1388 clock-names = "aclk", "pclk";
1391 #iommu-cells = <0>;
1392 power-domains = <&pd_mscl>;
1396 compatible = "samsung,exynos-sysmmu";
1399 clock-names = "aclk", "pclk";
1402 #iommu-cells = <0>;
1403 power-domains = <&pd_mfc>;
1407 compatible = "samsung,exynos-sysmmu";
1410 clock-names = "aclk", "pclk";
1413 #iommu-cells = <0>;
1414 power-domains = <&pd_mfc>;
1418 compatible = "samsung,exynos5433-uart";
1423 clock-names = "uart", "clk_uart_baud0";
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&uart0_bus>;
1430 compatible = "samsung,exynos5433-uart";
1435 clock-names = "uart", "clk_uart_baud0";
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&uart1_bus>;
1442 compatible = "samsung,exynos5433-uart";
1447 clock-names = "uart", "clk_uart_baud0";
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&uart2_bus>;
1454 compatible = "samsung,exynos5433-spi";
1458 dma-names = "tx", "rx";
1459 #address-cells = <1>;
1460 #size-cells = <0>;
1464 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1465 samsung,spi-src-clk = <0>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&spi0_bus>;
1468 num-cs = <1>;
1473 compatible = "samsung,exynos5433-spi";
1477 dma-names = "tx", "rx";
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1483 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1484 samsung,spi-src-clk = <0>;
1485 pinctrl-names = "default";
1486 pinctrl-0 = <&spi1_bus>;
1487 num-cs = <1>;
1492 compatible = "samsung,exynos5433-spi";
1496 dma-names = "tx", "rx";
1497 #address-cells = <1>;
1498 #size-cells = <0>;
1502 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1503 samsung,spi-src-clk = <0>;
1504 pinctrl-names = "default";
1505 pinctrl-0 = <&spi2_bus>;
1506 num-cs = <1>;
1511 compatible = "samsung,exynos5433-spi";
1515 dma-names = "tx", "rx";
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1521 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1522 samsung,spi-src-clk = <0>;
1523 pinctrl-names = "default";
1524 pinctrl-0 = <&spi3_bus>;
1525 num-cs = <1>;
1530 compatible = "samsung,exynos5433-spi";
1534 dma-names = "tx", "rx";
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1540 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1541 samsung,spi-src-clk = <0>;
1542 pinctrl-names = "default";
1543 pinctrl-0 = <&spi4_bus>;
1544 num-cs = <1>;
1549 compatible = "samsung,exynos7-adc";
1552 clock-names = "adc";
1554 #io-channel-cells = <1>;
1559 compatible = "samsung,exynos7-i2s";
1562 dma-names = "tx", "rx";
1567 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1568 #clock-cells = <1>;
1569 #sound-dai-cells = <1>;
1574 compatible = "samsung,exynos4210-pwm";
1581 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1583 clock-names = "timers";
1584 #pwm-cells = <3>;
1589 compatible = "samsung,exynos7-hsi2c";
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1594 pinctrl-names = "default";
1595 pinctrl-0 = <&hs_i2c0_bus>;
1597 clock-names = "hsi2c";
1602 compatible = "samsung,exynos7-hsi2c";
1605 #address-cells = <1>;
1606 #size-cells = <0>;
1607 pinctrl-names = "default";
1608 pinctrl-0 = <&hs_i2c1_bus>;
1610 clock-names = "hsi2c";
1615 compatible = "samsung,exynos7-hsi2c";
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1620 pinctrl-names = "default";
1621 pinctrl-0 = <&hs_i2c2_bus>;
1623 clock-names = "hsi2c";
1628 compatible = "samsung,exynos7-hsi2c";
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1633 pinctrl-names = "default";
1634 pinctrl-0 = <&hs_i2c3_bus>;
1636 clock-names = "hsi2c";
1641 compatible = "samsung,exynos7-hsi2c";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1646 pinctrl-names = "default";
1647 pinctrl-0 = <&hs_i2c4_bus>;
1649 clock-names = "hsi2c";
1654 compatible = "samsung,exynos7-hsi2c";
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659 pinctrl-names = "default";
1660 pinctrl-0 = <&hs_i2c5_bus>;
1662 clock-names = "hsi2c";
1667 compatible = "samsung,exynos7-hsi2c";
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1672 pinctrl-names = "default";
1673 pinctrl-0 = <&hs_i2c6_bus>;
1675 clock-names = "hsi2c";
1680 compatible = "samsung,exynos7-hsi2c";
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1685 pinctrl-names = "default";
1686 pinctrl-0 = <&hs_i2c7_bus>;
1688 clock-names = "hsi2c";
1693 compatible = "samsung,exynos7-hsi2c";
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&hs_i2c8_bus>;
1701 clock-names = "hsi2c";
1706 compatible = "samsung,exynos7-hsi2c";
1709 #address-cells = <1>;
1710 #size-cells = <0>;
1711 pinctrl-names = "default";
1712 pinctrl-0 = <&hs_i2c9_bus>;
1714 clock-names = "hsi2c";
1719 compatible = "samsung,exynos7-hsi2c";
1722 #address-cells = <1>;
1723 #size-cells = <0>;
1724 pinctrl-names = "default";
1725 pinctrl-0 = <&hs_i2c10_bus>;
1727 clock-names = "hsi2c";
1732 compatible = "samsung,exynos7-hsi2c";
1735 #address-cells = <1>;
1736 #size-cells = <0>;
1737 pinctrl-names = "default";
1738 pinctrl-0 = <&hs_i2c11_bus>;
1740 clock-names = "hsi2c";
1745 compatible = "samsung,exynos5433-dwusb3";
1750 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1751 #address-cells = <1>;
1752 #size-cells = <1>;
1761 clock-names = "ref", "bus_early", "suspend";
1765 phy-names = "usb2-phy", "usb3-phy";
1770 compatible = "samsung,exynos5433-usbdrd-phy";
1776 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1778 #phy-cells = <1>;
1779 samsung,pmu-syscon = <&pmu_system_controller>;
1784 compatible = "samsung,exynos5433-usbdrd-phy";
1790 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1792 #phy-cells = <1>;
1793 samsung,pmu-syscon = <&pmu_system_controller>;
1798 compatible = "samsung,exynos5433-dwusb3";
1803 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1804 #address-cells = <1>;
1805 #size-cells = <1>;
1814 clock-names = "ref", "bus_early", "suspend";
1818 phy-names = "usb2-phy", "usb3-phy";
1823 compatible = "samsung,exynos7-dw-mshc-smu";
1825 #address-cells = <1>;
1826 #size-cells = <0>;
1830 clock-names = "biu", "ciu";
1831 fifo-depth = <0x40>;
1836 compatible = "samsung,exynos7-dw-mshc-smu";
1838 #address-cells = <1>;
1839 #size-cells = <0>;
1843 clock-names = "biu", "ciu";
1844 fifo-depth = <0x40>;
1849 compatible = "samsung,exynos7-dw-mshc-smu";
1851 #address-cells = <1>;
1852 #size-cells = <0>;
1856 clock-names = "biu", "ciu";
1857 fifo-depth = <0x40>;
1866 clock-names = "apb_pclk";
1867 #dma-cells = <1>;
1868 #dma-channels = <8>;
1869 #dma-requests = <32>;
1877 clock-names = "apb_pclk";
1878 #dma-cells = <1>;
1879 #dma-channels = <8>;
1880 #dma-requests = <32>;
1883 audio-subsystem@11400000 {
1884 compatible = "samsung,exynos5433-lpass";
1887 clock-names = "sfr0_ctrl";
1888 samsung,pmu-syscon = <&pmu_system_controller>;
1889 power-domains = <&pd_aud>;
1890 #address-cells = <1>;
1891 #size-cells = <1>;
1899 clock-names = "apb_pclk";
1900 #dma-cells = <1>;
1901 #dma-channels = <8>;
1902 #dma-requests = <32>;
1903 power-domains = <&pd_aud>;
1907 compatible = "samsung,exynos7-i2s";
1910 dma-names = "tx", "rx";
1912 #address-cells = <1>;
1913 #size-cells = <0>;
1917 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1918 #clock-cells = <1>;
1919 pinctrl-names = "default";
1920 pinctrl-0 = <&i2s0_bus>;
1921 power-domains = <&pd_aud>;
1922 #sound-dai-cells = <1>;
1927 compatible = "samsung,exynos5433-uart";
1932 clock-names = "uart", "clk_uart_baud0";
1933 pinctrl-names = "default";
1934 pinctrl-0 = <&uart_aud_bus>;
1935 power-domains = <&pd_aud>;
1940 pcie_phy: pcie-phy@15680000 {
1941 compatible = "samsung,exynos5433-pcie-phy";
1943 samsung,pmu-syscon = <&pmu_system_controller>;
1944 samsung,fsys-sysreg = <&syscon_fsys>;
1945 #phy-cells = <0>;
1950 compatible = "samsung,exynos5433-pcie";
1953 reg-names = "dbi", "elbi", "config";
1954 #address-cells = <3>;
1955 #size-cells = <2>;
1956 #interrupt-cells = <1>;
1961 clock-names = "pcie", "pcie_bus";
1962 num-lanes = <1>;
1963 num-viewport = <3>;
1964 bus-range = <0x00 0xff>;
1973 compatible = "arm,armv8-timer";
1985 #include "exynos5433-bus.dtsi"
1986 #include "exynos5433-pinctrl.dtsi"
1987 #include "exynos5433-tmu.dtsi"