Lines Matching +full:cortex +full:- +full:a57
1 # SPDX-License-Identifier: GPL-2.0-only
177 if $(cc-option,-fpatchable-function-entry=2)
225 ARM 64-bit (AArch64) Linux support.
257 # VA_BITS - PAGE_SHIFT - 3
336 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
363 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
368 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
371 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
377 data cache clean-and-invalidate.
385 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
390 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
399 data cache clean-and-invalidate.
407 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
412 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
415 If a Cortex-A53 processor is executing a store or prefetch for
422 data cache clean-and-invalidate.
430 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
435 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
444 data cache clean-and-invalidate.
452 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
456 erratum 832075 on Cortex-A57 parts up to r1p2.
458 Affected Cortex-A57 parts might deadlock when exclusive load/store
459 instructions to Write-Back memory are mixed with Device loads.
461 The workaround is to promote device loads to use Load-Acquire
470 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
475 erratum 834220 on Cortex-A57 parts up to r1p2.
477 Affected Cortex-A57 parts might report a Stage 2 translation
491 bool "Cortex-A53: 845719: a load might read incorrect data"
496 erratum 845719 on Cortex-A53 parts up to r0p4.
498 When running a compat (AArch32) userspace on an affected Cortex-A53
504 return to a 32-bit task.
512 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
516 This option links the kernel with '--fix-cortex-a53-843419' and
519 Cortex-A53 parts up to r0p4.
524 def_bool $(ld-option,--fix-cortex-a53-843419)
527 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
530 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
532 Affected Cortex-A55 cores (all revisions) could cause incorrect
534 without a break-before-make. The workaround is to disable the usage
541 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
545 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
548 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
558 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
562 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
564 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
571 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
575 This option adds work arounds for ARM Cortex-A57 erratum 1319537
578 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
584 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
588 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
590 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
600 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
604 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
606 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
610 break-before-make sequence, then under very rare circumstances
616 bool "Cortex-A76: Software Step might prevent interrupt recognition"
619 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
621 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
634 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
637 This option adds a workaround for ARM Neoverse-N1 erratum
640 Affected Neoverse-N1 cores could execute a stale instruction when
645 forces user-space to perform cache maintenance.
650 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
653 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
655 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
656 of a store-exclusive or read of PAR_EL1 and a load with device or
657 non-cacheable memory attributes. The workaround depends on a firmware
675 This implements two gicv3-its errata workarounds for ThunderX. Both
711 contains data for a non-current ASID. The fix is to
722 interrupts in host. Trapping both GICv3 group-0 and group-1
745 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
748 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
749 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
753 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
754 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
755 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
756 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
759 The workaround only affects the Fujitsu-A64FX.
819 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
826 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
830 MSI doorbell writes with non-zero values for the device ID.
860 look-up. AArch32 emulation requires applications compiled
876 bool "36-bit" if EXPERT
880 bool "39-bit"
884 bool "42-bit"
888 bool "47-bit"
892 bool "48-bit"
895 bool "52-bit"
898 Enable 52-bit virtual addressing for userspace when explicitly
899 requested via a hint to mmap(). The kernel will also use 52-bit
901 this feature is available, otherwise it reverts to 48-bit).
903 NOTE: Enabling 52-bit virtual addressing in conjunction with
906 impact on its susceptibility to brute-force attacks.
908 If unsure, select 48-bit virtual addressing instead.
913 bool "Force 52-bit virtual addresses for userspace"
916 For systems with 52-bit userspace VAs enabled, the kernel will attempt
917 to maintain compatibility with older software by providing 48-bit VAs
920 This configuration option disables the 48-bit compatibility logic, and
921 forces all userspace addresses to be 52-bit on HW that supports it. One
942 bool "48-bit"
945 bool "52-bit (ARMv8.2)"
949 Enable support for a 52-bit physical address space, introduced as
950 part of the ARMv8.2-LPA extension.
953 do not support ARMv8.2-LPA, but with some added memory overhead (and
972 bool "Build big-endian kernel"
975 Say Y if you plan on running a kernel with a big-endian userspace.
978 bool "Build little-endian kernel"
980 Say Y if you plan on running a kernel with a little-endian userspace.
986 bool "Multi-core scheduler support"
988 Multi-core scheduler support improves the CPU scheduler's decision
989 making when dealing with multi-core CPU chips at a cost of slightly
1000 int "Maximum number of CPUs (2-4096)"
1005 bool "Support for hot-pluggable CPUs"
1018 Enable NUMA (Non-Uniform Memory Access) support.
1061 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1130 loaded in the main kernel with kexec-tools into a specially
1134 For more details see Documentation/admin-guide/kdump/kdump.rst
1170 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1179 Speculation attacks against some high-performance processors can
1191 Apply read-only attributes of VM areas to the linear alias of
1192 the backing pages as well. This prevents code or read-only data
1205 user-space memory directly by pointing TTBR0_EL1 to a reserved
1216 Documentation/arm64/tagged-address-abi.rst.
1219 bool "Kernel support for 32-bit EL0"
1225 This option enables support for a 32-bit EL0 running under a 64-bit
1226 kernel at EL1. AArch32-specific components such as system calls,
1234 If you want to execute 32-bit userspace applications, say Y.
1239 bool "Enable kuser helpers page for 32-bit applications"
1242 Warning: disabling this option may break 32-bit user programs.
1266 bool "Enable vDSO for 32-bit applications"
1271 Place in the process address space of 32-bit applications an
1275 You must have a 32-bit build of glibc 2.22 or later for programs
1279 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1283 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1284 otherwise with '-marm'.
1326 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1327 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1342 The SETEND instruction alters the data-endianness of the
1350 for this feature to be enabled. If a new CPU - which doesn't support mixed
1351 endian - is hotplugged in after this feature has been enabled, there could
1370 Similarly, writes to read-only pages with the DBM bit set will
1371 clear the read-only bit (AP[2]) instead of raising a
1375 to work on pre-ARMv8.1 hardware and the performance impact is
1383 prevents the kernel or hypervisor from accessing user-space (EL0)
1393 def_bool $(as-instr,.arch_extension rcpc)
1396 def_bool $(as-instr,.arch_extension lse)
1412 Say Y here to make use of these instructions for the in-kernel
1480 context-switched along with the process.
1503 If the compiler supports the -mbranch-protection or
1504 -msign-return-address flag (e.g. GCC 7 or later), then this option
1515 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1519 def_bool $(cc-option,-msign-return-address=all)
1522 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1525 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1555 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1562 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1573 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1605 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1616 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1640 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1644 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1657 architectural support for run-time, always-on detection of
1659 to eliminate vulnerabilities arising from memory-unsafe
1667 not be allowed a late bring-up.
1673 Documentation/arm64/memory-tagging-extension.rst.
1685 Access Never to be used with Execute-only mappings.
1716 If you need the kernel to boot on SVE-capable hardware with broken
1743 bool "Support for NMI-like interrupts"
1746 Adds support for mimicking Non-Maskable Interrupts through the use of
1790 random u64 value in /chosen/kaslr-seed at kernel entry.
1818 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
1841 Provide a set of default command-line options at build time by
1855 Uses the command-line options passed by the boot loader. If
1865 command-line options your boot loader passes to the kernel.
1887 by UEFI firmware (such as non-volatile variables, realtime
1901 continue to boot on existing non-UEFI platforms.