47 	__asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));  in tauros2_clean_pa()
52 	__asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));  in tauros2_clean_inv_pa()
57 	__asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));  in tauros2_inv_pa()
123 	"mcr	p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"  in tauros2_disable()
124 	"mrc	p15, 0, %0, c1, c0, 0\n\t"  in tauros2_disable()
125 	"bic	%0, %0, #(1 << 26)\n\t"  in tauros2_disable()
126 	"mcr	p15, 0, %0, c1, c0, 0  @Disable L2 Cache\n\t"  in tauros2_disable()
127 	: : "r" (0x0));  in tauros2_disable()
133 	"mcr	p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"  in tauros2_resume()
134 	"mrc	p15, 0, %0, c1, c0, 0\n\t"  in tauros2_resume()
135 	"orr	%0, %0, #(1 << 26)\n\t"  in tauros2_resume()
136 	"mcr	p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"  in tauros2_resume()
137 	: : "r" (0x0));  in tauros2_resume()
145 	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));  in read_extra_features()
152 	__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));  in write_extra_features()
157 	return !!((processor_id & 0x000f0000) == 0x000f0000);  in cpuid_scheme()
164 	__asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));  in read_mmfr3()
173 	__asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));  in read_actlr()
180 	__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));  in write_actlr()
215 	if ((processor_id & 0xff0f0000) == 0x56050000) {  in tauros2_internal_init()
223 		if (!(feat & 0x00400000)) {  in tauros2_internal_init()
225 			write_extra_features(feat | 0x00400000);  in tauros2_internal_init()
250 	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {  in tauros2_internal_init()
260 		if (!(actlr & 0x00000002)) {  in tauros2_internal_init()
262 			write_actlr(actlr | 0x00000002);  in tauros2_internal_init()
300 			features = 0;  in tauros2_init()