Lines Matching +full:system +full:- +full:cache +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
208 # ARM1020 - needs validating
222 with an addition of a floating-point unit.
227 # ARM1020E - needs validating
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
260 # ARM1026EJ-S
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
275 Say Y if you want support for the ARM1026EJ-S processor.
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
296 Say Y if you want support for the SA-110 processor.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
521 # The cache model
553 # The copy-page model
573 ARM Architecture Version 4 TLB with writethrough cache.
578 ARM Architecture Version 4 TLB with writeback cache.
583 ARM Architecture Version 4 TLB with writeback cache and invalidate
584 instruction cache entry.
589 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
594 Faraday ARM FA526 architecture, unified TLB with writeback cache
595 and invalidate instruction cache entry. Branch target buffer is
610 tag TLB and possibly cache entries.
644 by the system, but must not be lower.
646 interrupts supported by the NVIC on Cortex-M family.
651 # CPU supports 36-bit I/O
706 Extensions to install hypervisors without run-time firmware
734 monitor to maintain update atomicity. If your system does not
741 bool "Build big-endian kernel"
745 Say Y if you plan on running a kernel in big-endian mode.
747 port must properly enable any big-endian related features
755 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
762 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
776 bool "Disable I-Cache (I-bit)"
779 Say Y here to disable the processor instruction cache. Unless
783 bool "Workaround for I-Cache line size mismatch between CPU cores"
786 Some big.LITTLE systems have I-Cache line size mismatch between
788 proper I-Cache support on such systems. If unsure, say N.
791 bool "Disable D-Cache (C-bit)"
794 Say Y here to disable the processor data cache. Unless
801 default 0x00002000 # default size for ARM946E-S
803 Some cores are synthesizable to have various sized cache. For
804 ARM946E-S case, it can vary from 0KB to 1MB.
805 To support such cache operations, it is efficient to know the size
811 bool "Force write through D-cache"
815 Say Y here to use the data cache in writethrough mode. Unless you
819 bool "Round robin I and D cache replacement algorithm"
822 Say Y here to use the predictable round-robin cache replacement
839 Speculation attacks against some high-performance processors rely
846 This config option will take CPU-specific actions to harden
849 the system firmware.
857 An SMP system using a pre-ARMv6 processor (there are apparently
874 the CPU type fitted to the system. This permits binaries to be
894 bool "Enable VDSO for acceleration of some system calls"
911 bool "Enable read/write for ownership DMA cache maintenance"
916 cache maintenance operations and the dma_{map,unmap}_area()
917 functions may leave stale cache entries on other CPUs. By
919 DMA cache maintenance functions is performed. These LDR/STR
920 instructions change the cache line state to shared or modified
921 so that the cache operation has the desired effect.
924 not perform speculative loads into the D-cache. For such
925 processors, if cache maintenance operations are not broadcast
926 in hardware, other workarounds are needed (e.g. cache
936 The outer cache has a outer_cache_fns.sync function pointer
937 that can be used to drain the write buffer of the outer cache.
940 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
944 This option enables the Broadcom Brahma-B15 read-ahead cache
945 controller. If disabled, the read-ahead cache remains off.
948 bool "Enable the Feroceon L2 cache controller"
953 This option enables the Feroceon L2 cache controller.
956 bool "Force Feroceon L2 cache write through"
959 Say Y here to use the Feroceon L2 cache in writethrough mode.
966 or PL310 cache controller, but where its use is optional.
971 Boards or SoCs which always require the cache controller
977 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
989 of the L220 and PL310 outer cache controllers.
996 The PL310 L2 cache controller implements three types of Clean &
1008 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1017 bool "PL310 errata: cache sync operation may be faulty"
1021 Under some condition the effect of cache sync operation on
1025 is to replace the normal offset of cache sync operation (0x730)
1027 This has the same effect as the cache sync operation: store buffer
1034 not automatically drain. This can cause normal, non-cacheable
1035 writes to be retained when the memory system is idle, leading
1038 on systems with an outer cache, the store buffer is drained
1044 bool "Enable the Tauros2 L2 cache controller"
1049 This option enables the Tauros2 L2 cache controller (as
1053 bool "Enable the UniPhier outer cache controller"
1059 This option enables the UniPhier outer cache (system cache)
1060 controller.
1063 bool "Enable the L2 cache on XScale3"
1068 This option enables the L2 cache on XScale3.
1074 Setting ARM L1 cache line size to 64 Bytes.
1079 Setting ARM L1 cache line size to 128 Bytes.
1088 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1104 On some of the beefier ARMv7-M machines (with DMA and write
1120 bool "Make rodata strictly non-executable"
1124 If this is set, rodata will be made explicitly non-executable. This
1127 additional section-aligned split of rodata from kernel text so it
1128 can be made explicitly non-executable. This padding may waste memory