Lines Matching +full:embedded +full:- +full:trace +full:- +full:extension
1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
208 # ARM1020 - needs validating
222 with an addition of a floating-point unit.
227 # ARM1020E - needs validating
255 embedded trace macrocell, and a floating-point unit.
260 # ARM1026EJ-S
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
275 Say Y if you want support for the ARM1026EJ-S processor.
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
296 Say Y if you want support for the SA-110 processor.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
553 # The copy-page model
589 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
646 interrupts supported by the NVIC on Cortex-M family.
651 # CPU supports 36-bit I/O
659 bool "Support for the Large Physical Address Extension"
668 processors without the LPA extension.
695 bool "Enable ThumbEE CPU extension"
698 Say Y here if you have a CPU with the ThumbEE extension and code to
706 Extensions to install hypervisors without run-time firmware
741 bool "Build big-endian kernel"
745 Say Y if you plan on running a kernel in big-endian mode.
747 port must properly enable any big-endian related features
755 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
762 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
776 bool "Disable I-Cache (I-bit)"
783 bool "Workaround for I-Cache line size mismatch between CPU cores"
786 Some big.LITTLE systems have I-Cache line size mismatch between
788 proper I-Cache support on such systems. If unsure, say N.
791 bool "Disable D-Cache (C-bit)"
801 default 0x00002000 # default size for ARM946E-S
804 ARM946E-S case, it can vary from 0KB to 1MB.
811 bool "Force write through D-cache"
822 Say Y here to use the predictable round-robin cache replacement
839 Speculation attacks against some high-performance processors rely
846 This config option will take CPU-specific actions to harden
857 An SMP system using a pre-ARMv6 processor (there are apparently
924 not perform speculative loads into the D-cache. For such
940 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
944 This option enables the Broadcom Brahma-B15 read-ahead cache
945 controller. If disabled, the read-ahead cache remains off.
1034 not automatically drain. This can cause normal, non-cacheable
1088 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1104 On some of the beefier ARMv7-M machines (with DMA and write
1120 bool "Make rodata strictly non-executable"
1124 If this is set, rodata will be made explicitly non-executable. This
1127 additional section-aligned split of rodata from kernel text so it
1128 can be made explicitly non-executable. This padding may waste memory