Lines Matching +full:tegra30 +full:- +full:emc

1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
190  * Puts the current CPU in wait-for-event mode on the flow controller
191  * and powergates it -- flags (in R0) indicate the request type.
194  * corrupts r0-r4, r10-r12
199 	cmp	r10, #TEGRA30
200 	bne	_no_cpu0_chk	@ It's not Tegra30
219 	cmp	r10, #TEGRA30
244 	cmp	r10, #TEGRA30
250 	cmp	r10, #TEGRA30
291 	 * CPU power-gating process, to avoid loading from SDRAM which
292 	 * are not supported once SDRAM is put into self-refresh.
294 	 * disabled before putting SDRAM into self-refresh to avoid
354  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
378 	cmp	r10, #TEGRA30
419 	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
423 	cmp	r1, #TEGRA30
460 	cmp	r10, #TEGRA30
461 	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
507 	cmp	r10, #TEGRA30
527 	/* Issue a ZQ_CAL for dev0 - DDR3 */
537 	/* Issue a ZQ_CAL for dev1 - DDR3 */
546 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
556 	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
573 	/* Tegra114 had dual EMC channel, now config the other one */
628 	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
631 	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
635 	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
646  * puts memory in self-refresh for LP0 and LP1
690 	/* store enable-state of PLLs */
705 	cmp	r1, #TEGRA30
724 	cmp	r10, #TEGRA30
757 	cmp	r10, #TEGRA30
767 	cmp	r10, #TEGRA30
792 	cmp	r10, #TEGRA30
817 	cmp	r10, #TEGRA30
818 	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
825 	cmp	r10, #TEGRA30
862 	bne	emcself			@ loop until DDR in self-refresh
870 	cmp	r10, #TEGRA30
877 	/* Tegra114 had dual EMC channel, now config the other one */