Lines Matching refs:parent_irq
46 unsigned long parent_irq; member
94 parent_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c_irq_mask()
102 irq_data->parent_irq); in s3c_irq_mask()
122 irq_data->parent_irq); in s3c_irq_unmask()
469 if (irq_data->parent_irq > 31) { in s3c24xx_irq_map()
471 irq_data->parent_irq); in s3c24xx_irq_map()
475 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_map()
481 irq_data->parent_irq); in s3c24xx_irq_map()
484 irq_data->parent_irq); in s3c24xx_irq_map()
612 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
619 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
620 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
679 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
680 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
681 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
740 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
776 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
777 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
842 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
843 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
851 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
852 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
870 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
945 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
947 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
953 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
954 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
955 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
956 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1020 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1028 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1029 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1030 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1031 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1032 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1094 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1103 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1104 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1199 irq_data->parent_irq = intspec[1]; in s3c24xx_irq_xlate_of()
1200 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_xlate_of()