1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2006-2008 Simtec Electronics
12 #include <linux/ioport.h>
27 #include <linux/soc/samsung/s3c-cpufreq-core.h>
34  * s3c2412_print_timing - print timing information via printk.
41 	unsigned int bank;  in s3c2412_print_timing()  local
43 	for (bank = 0; bank < MAX_BANKS; bank++) {  in s3c2412_print_timing()
44 		bt = iot->bank[bank].io_2412;  in s3c2412_print_timing()
49 		       "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,  in s3c2412_print_timing()
50 		       print_ns(bt->idcy),  in s3c2412_print_timing()
51 		       print_ns(bt->wstrd),  in s3c2412_print_timing()
52 		       print_ns(bt->wstwr),  in s3c2412_print_timing()
53 		       print_ns(bt->wstoen),  in s3c2412_print_timing()
54 		       print_ns(bt->wstwen),  in s3c2412_print_timing()
55 		       print_ns(bt->wstbrd));  in s3c2412_print_timing()
60  * to_div - turn a cycle length into a divisor setting.
70  * calc_timing - calculate timing divisor value and check in range.
81 		*err = -EINVAL;  in calc_timing()
87  * s3c2412_calc_bank - calculate the bank divisor settings.
89  * @bt: The bank timing.
94 	unsigned int hclk = cfg->freq.hclk_tns;  in s3c2412_calc_bank()
97 	bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);  in s3c2412_calc_bank()
98 	bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);  in s3c2412_calc_bank()
99 	bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);  in s3c2412_calc_bank()
100 	bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);  in s3c2412_calc_bank()
101 	bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);  in s3c2412_calc_bank()
102 	bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);  in s3c2412_calc_bank()
108  * s3c2412_iotiming_debugfs - debugfs show io bank timing information
111  * @iob: The IO bank information to decode.
117 	struct s3c2412_iobank_timing *bt = iob->io_2412;  in s3c2412_iotiming_debugfs()
122 		   print_ns(bt->idcy),  in s3c2412_iotiming_debugfs()
123 		   print_ns(bt->wstrd),  in s3c2412_iotiming_debugfs()
124 		   print_ns(bt->wstwr),  in s3c2412_iotiming_debugfs()
125 		   print_ns(bt->wstoen),  in s3c2412_iotiming_debugfs()
126 		   print_ns(bt->wstwen),  in s3c2412_iotiming_debugfs()
127 		   print_ns(bt->wstbrd));  in s3c2412_iotiming_debugfs()
131  * s3c2412_iotiming_calc - calculate all the bank divisor settings.
133  * @iot: The bank timing information.
142 	int bank;  in s3c2412_iotiming_calc()  local
145 	for (bank = 0; bank < MAX_BANKS; bank++) {  in s3c2412_iotiming_calc()
146 		bt = iot->bank[bank].io_2412;  in s3c2412_iotiming_calc()
152 			printk(KERN_ERR "%s: cannot calculate bank %d io\n",  in s3c2412_iotiming_calc()
153 			       __func__, bank);  in s3c2412_iotiming_calc()
164  * s3c2412_iotiming_set - set the timing information
166  * @iot: The bank timing information.
168  * Set the IO bank information from the details calculated earlier from
176 	int bank;  in s3c2412_iotiming_set()  local
180 	for (bank = 0; bank < MAX_BANKS; bank++) {  in s3c2412_iotiming_set()
181 		bt = iot->bank[bank].io_2412;  in s3c2412_iotiming_set()
185 		regs = S3C2412_SSMC_BANK(bank);  in s3c2412_iotiming_set()
187 		__raw_writel(bt->smbidcyr, regs + SMBIDCYR);  in s3c2412_iotiming_set()
188 		__raw_writel(bt->smbwstrd, regs + SMBWSTRDR);  in s3c2412_iotiming_set()
189 		__raw_writel(bt->smbwstwr, regs + SMBWSTWRR);  in s3c2412_iotiming_set()
190 		__raw_writel(bt->smbwstoen, regs + SMBWSTOENR);  in s3c2412_iotiming_set()
191 		__raw_writel(bt->smbwstwen, regs + SMBWSTWENR);  in s3c2412_iotiming_set()
192 		__raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);  in s3c2412_iotiming_set()
203 				     unsigned int bank)  in s3c2412_iotiming_getbank()  argument
205 	unsigned long clk = cfg->freq.hclk_tns;  /* ssmc clock??? */  in s3c2412_iotiming_getbank()
206 	void __iomem *regs = S3C2412_SSMC_BANK(bank);  in s3c2412_iotiming_getbank()
208 	bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));  in s3c2412_iotiming_getbank()
209 	bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));  in s3c2412_iotiming_getbank()
210 	bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));  in s3c2412_iotiming_getbank()
211 	bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));  in s3c2412_iotiming_getbank()
212 	bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));  in s3c2412_iotiming_getbank()
216  * bank_is_io - return true if bank is (possibly) IO.
217  * @bank: The bank number.
220 static inline bool bank_is_io(unsigned int bank, u32 bankcfg)  in bank_is_io()  argument
222 	if (bank < 2)  in bank_is_io()
225 	return !(bankcfg & (1 << bank));  in bank_is_io()
233 	unsigned int bank;  in s3c2412_iotiming_get()  local
237 	for (bank = 0; bank < MAX_BANKS; bank++) {  in s3c2412_iotiming_get()
238 		if (!bank_is_io(bank, bankcfg))  in s3c2412_iotiming_get()
243 			return -ENOMEM;  in s3c2412_iotiming_get()
245 		timings->bank[bank].io_2412 = bt;  in s3c2412_iotiming_get()
246 		s3c2412_iotiming_getbank(cfg, bt, bank);  in s3c2412_iotiming_get()
259 	struct s3c_cpufreq_board *board = cfg->board;  in s3c2412_cpufreq_setrefresh()
271 	refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);  in s3c2412_cpufreq_setrefresh()
273 	refresh &= ((1 << 16) - 1);  in s3c2412_cpufreq_setrefresh()