Lines Matching +full:bank +full:- +full:ioport
1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
22 #include <linux/ioport.h>
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
43 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
58 void __iomem *reg = chip->base + 0x08; in samsung_gpio_getpull_updown()
112 void __iomem *reg = chip->base + 0x08; in s3c24xx_gpio_setpull_1()
120 return -EINVAL; in s3c24xx_gpio_setpull_1()
130 void __iomem *reg = chip->base + 0x08; in s3c24xx_gpio_getpull_1()
162 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
178 void __iomem *reg = chip->base; in samsung_gpio_setcfg_2bit()
185 return -EINVAL; in samsung_gpio_setcfg_2bit()
199 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
213 con = __raw_readl(chip->base); in samsung_gpio_getcfg_2bit()
222 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
231 * others = Special functions (dependent on bank)
241 void __iomem *reg = chip->base; in samsung_gpio_setcfg_4bit()
245 if (off < 8 && chip->chip.ngpio > 8) in samsung_gpio_setcfg_4bit()
246 reg -= 4; in samsung_gpio_setcfg_4bit()
262 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
276 void __iomem *reg = chip->base; in samsung_gpio_getcfg_4bit()
280 if (off < 8 && chip->chip.ngpio > 8) in samsung_gpio_getcfg_4bit()
281 reg -= 4; in samsung_gpio_getcfg_4bit()
293 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
306 void __iomem *reg = chip->base; in s3c24xx_gpio_setcfg_abank()
314 cfg -= 1; in s3c24xx_gpio_setcfg_abank()
316 return -EINVAL; in s3c24xx_gpio_setcfg_abank()
330 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
346 con = __raw_readl(chip->base); in s3c24xx_gpio_getcfg_abank()
358 for (; nr_chips > 0; nr_chips--, chipcfg++) { in samsung_gpiolib_set_cfg()
359 if (!chipcfg->set_config) in samsung_gpiolib_set_cfg()
360 chipcfg->set_config = samsung_gpio_setcfg_4bit; in samsung_gpiolib_set_cfg()
361 if (!chipcfg->get_config) in samsung_gpiolib_set_cfg()
362 chipcfg->get_config = samsung_gpio_getcfg_4bit; in samsung_gpiolib_set_cfg()
363 if (!chipcfg->set_pull) in samsung_gpiolib_set_cfg()
364 chipcfg->set_pull = samsung_gpio_setpull_updown; in samsung_gpiolib_set_cfg()
365 if (!chipcfg->get_pull) in samsung_gpiolib_set_cfg()
366 chipcfg->get_pull = samsung_gpio_getpull_updown; in samsung_gpiolib_set_cfg()
418 * GPIO functions which deal with the case where each gpio bank of the
423 * 00 = input, 01 = output, others mean special-function
431 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_input()
450 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_output()
481 * 0000 = input, 0001 = output, others mean special-function
494 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_input()
498 if (ourchip->bitmap_gpio_int & BIT(offset)) in samsung_gpiolib_4bit_input()
513 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_output()
540 * bank has more than 8 GPIOs.
547 * 0000 = input, 0001 = output, others mean special-function
550 * 0000 = input, 0001 = output, others mean special-function
556 * the data register at ourchip->base + 0x04.
563 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_input()
568 offset -= 8; in samsung_gpiolib_4bit2_input()
570 regcon -= 4; in samsung_gpiolib_4bit2_input()
585 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_output()
592 con_offset -= 8; in samsung_gpiolib_4bit2_output()
594 regcon -= 4; in samsung_gpiolib_4bit2_output()
617 /* The next set of routines are for the case of s3c24xx bank a */
621 return -EINVAL; in s3c24xx_gpiolib_banka_input()
628 void __iomem *base = ourchip->base; in s3c24xx_gpiolib_banka_output()
658 void __iomem *base = ourchip->base; in samsung_gpiolib_set()
678 val = __raw_readl(ourchip->base + 0x04); in samsung_gpiolib_get()
705 gpn = chip->chip.base; in s3c_gpiolib_track()
706 for (i = 0; i < chip->chip.ngpio; i++, gpn++) { in s3c_gpiolib_track()
714 * samsung_gpiolib_add() - add the Samsung gpio_chip.
725 struct gpio_chip *gc = &chip->chip; in samsung_gpiolib_add()
728 BUG_ON(!chip->base); in samsung_gpiolib_add()
729 BUG_ON(!gc->label); in samsung_gpiolib_add()
730 BUG_ON(!gc->ngpio); in samsung_gpiolib_add()
732 spin_lock_init(&chip->lock); in samsung_gpiolib_add()
734 if (!gc->direction_input) in samsung_gpiolib_add()
735 gc->direction_input = samsung_gpiolib_2bit_input; in samsung_gpiolib_add()
736 if (!gc->direction_output) in samsung_gpiolib_add()
737 gc->direction_output = samsung_gpiolib_2bit_output; in samsung_gpiolib_add()
738 if (!gc->set) in samsung_gpiolib_add()
739 gc->set = samsung_gpiolib_set; in samsung_gpiolib_add()
740 if (!gc->get) in samsung_gpiolib_add()
741 gc->get = samsung_gpiolib_get; in samsung_gpiolib_add()
744 if (chip->pm != NULL) { in samsung_gpiolib_add()
745 if (!chip->pm->save || !chip->pm->resume) in samsung_gpiolib_add()
747 gc->label); in samsung_gpiolib_add()
749 pr_err("gpio: %s has no PM function\n", gc->label); in samsung_gpiolib_add()
762 struct gpio_chip *gc = &chip->chip; in s3c24xx_gpiolib_add_chips()
766 if (chip->chip.base >= S3C_GPIO_END) in s3c24xx_gpiolib_add_chips()
769 if (!chip->config) in s3c24xx_gpiolib_add_chips()
770 chip->config = &s3c24xx_gpiocfg_default; in s3c24xx_gpiolib_add_chips()
771 if (!chip->pm) in s3c24xx_gpiolib_add_chips()
772 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); in s3c24xx_gpiolib_add_chips()
773 if ((base != NULL) && (chip->base == NULL)) in s3c24xx_gpiolib_add_chips()
774 chip->base = base + ((i) * 0x10); in s3c24xx_gpiolib_add_chips()
776 if (!gc->direction_input) in s3c24xx_gpiolib_add_chips()
777 gc->direction_input = samsung_gpiolib_2bit_input; in s3c24xx_gpiolib_add_chips()
778 if (!gc->direction_output) in s3c24xx_gpiolib_add_chips()
779 gc->direction_output = samsung_gpiolib_2bit_output; in s3c24xx_gpiolib_add_chips()
792 chip->chip.direction_input = samsung_gpiolib_2bit_input; in samsung_gpiolib_add_2bit_chips()
793 chip->chip.direction_output = samsung_gpiolib_2bit_output; in samsung_gpiolib_add_2bit_chips()
795 if (!chip->config) in samsung_gpiolib_add_2bit_chips()
796 chip->config = &samsung_gpio_cfgs[7]; in samsung_gpiolib_add_2bit_chips()
797 if (!chip->pm) in samsung_gpiolib_add_2bit_chips()
798 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); in samsung_gpiolib_add_2bit_chips()
799 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_2bit_chips()
800 chip->base = base + ((i) * offset); in samsung_gpiolib_add_2bit_chips()
807 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
815 * others = Special functions (dependent on bank)
828 chip->chip.direction_input = samsung_gpiolib_4bit_input; in samsung_gpiolib_add_4bit_chips()
829 chip->chip.direction_output = samsung_gpiolib_4bit_output; in samsung_gpiolib_add_4bit_chips()
831 if (!chip->config) in samsung_gpiolib_add_4bit_chips()
832 chip->config = &samsung_gpio_cfgs[2]; in samsung_gpiolib_add_4bit_chips()
833 if (!chip->pm) in samsung_gpiolib_add_4bit_chips()
834 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); in samsung_gpiolib_add_4bit_chips()
835 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_4bit_chips()
836 chip->base = base + ((i) * 0x20); in samsung_gpiolib_add_4bit_chips()
838 chip->bitmap_gpio_int = 0; in samsung_gpiolib_add_4bit_chips()
847 for (; nr_chips > 0; nr_chips--, chip++) { in samsung_gpiolib_add_4bit2_chips()
848 chip->chip.direction_input = samsung_gpiolib_4bit2_input; in samsung_gpiolib_add_4bit2_chips()
849 chip->chip.direction_output = samsung_gpiolib_4bit2_output; in samsung_gpiolib_add_4bit2_chips()
851 if (!chip->config) in samsung_gpiolib_add_4bit2_chips()
852 chip->config = &samsung_gpio_cfgs[2]; in samsung_gpiolib_add_4bit2_chips()
853 if (!chip->pm) in samsung_gpiolib_add_4bit2_chips()
854 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); in samsung_gpiolib_add_4bit2_chips()
864 return samsung_chip->irq_base + offset; in samsung_gpiolib_to_irq()
878 return IRQ_EINT4 + offset - 4; in s3c24xx_gpiolib_fbank_to_irq()
880 return -EINVAL; in s3c24xx_gpiolib_fbank_to_irq()
887 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; in s3c64xx_gpiolib_mbank_to_irq()
892 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; in s3c64xx_gpiolib_lbank_to_irq()
999 * GPIO bank summary:
1001 * Bank GPIOs Style SlpCon ExtInt Group
1021 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1172 * pinctrl-samsung driver is used, providing both GPIO and pin control in samsung_gpiolib_init()
1173 * interfaces. For legacy (non-DT) platforms this driver is used. in samsung_gpiolib_init()
1208 return -EINVAL; in s3c_gpio_cfgpin()
1210 offset = pin - chip->chip.base; in s3c_gpio_cfgpin()
1225 for (; nr > 0; nr--, start++) { in s3c_gpio_cfgpin_range()
1240 for (; nr > 0; nr--, start++) { in s3c_gpio_cfgall_range()
1259 offset = pin - chip->chip.base; in s3c_gpio_getcfg()
1277 return -EINVAL; in s3c_gpio_setpull()
1279 offset = pin - chip->chip.base; in s3c_gpio_setpull()
1297 offset = pin - chip->chip.base; in s3c_gpio_getpull()