Lines Matching +full:0 +full:x00e00000
25 #define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */
26 #define BALLOON3_FPGA_LENGTH 0x01000000
28 #define BALLOON3_FPGA_SETnCLR (0x1000)
31 #define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
32 #define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
34 #define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c)
36 #define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000)
37 #define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
38 #define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
39 #define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
40 #define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
43 #define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C)
44 #define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c)
46 #define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000)
47 #define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004)
48 #define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c)
51 #define BALLOON3_CF_nIRQ (1 << 0)
55 #define BALLOON3_CF_RESET (1 << 0)
60 #define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
71 #define BALLOON3_NAND_CONTROL_FLCLE (1 << 0)
74 #define BALLOON3_NAND_STAT_RNB (1 << 0)
77 #define BALLOON3_NAND_CONTROL2_16BIT (1 << 0)
97 #define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0)
107 #define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */
108 #define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */
111 #define CPLD_LCD0_DATA_SET 0x00
112 #define CPLD_LCD0_DATA_CLR 0x10
113 #define CPLD_LCD0_COMMAND_SET 0x01
114 #define CPLD_LCD0_COMMAND_CLR 0x11
115 #define CPLD_LCD1_DATA_SET 0x02
116 #define CPLD_LCD1_DATA_CLR 0x12
117 #define CPLD_LCD1_COMMAND_SET 0x03
118 #define CPLD_LCD1_COMMAND_CLR 0x13
120 #define CPLD_MISC_SET 0x07
121 #define CPLD_MISC_CLR 0x17
122 #define CPLD_MISC_LOON_NRESET_BIT 0
129 #define CPLD_LCD_SET 0x08
130 #define CPLD_LCD_CLR 0x18
131 #define CPLD_LCD_BACKLIGHT_EN_0_BIT 0
137 #define CPLD_LCD_RO_SET 0x09
138 #define CPLD_LCD_RO_CLR 0x19
139 #define CPLD_LCD_RO_LCD0_nWAIT_BIT 0
142 #define CPLD_SERIAL_SET 0x0a
143 #define CPLD_SERIAL_CLR 0x1a
144 #define CPLD_SERIAL_GSM_RI_BIT 0
151 #define CPLD_SROUTING_SET 0x0b
152 #define CPLD_SROUTING_CLR 0x1b
153 #define CPLD_SROUTING_MSP430_LPR 0
156 #define CPLD_SROUTING_LOON_LPR (0 << 4)
160 #define CPLD_AROUTING_SET 0x0c
161 #define CPLD_AROUTING_CLR 0x1c
162 #define CPLD_AROUTING_MIC2PHONE_BIT 0