Lines Matching +full:0 +full:x0c00

42 #define CLKGEN_REG_ASM_BASE		OMAP1_IO_ADDRESS(0xfffece00)
43 #define ARM_IDLECT1_ASM_OFFSET		0x04
44 #define ARM_IDLECT2_ASM_OFFSET		0x08
46 #define TCMIF_ASM_BASE			OMAP1_IO_ADDRESS(0xfffecc00)
47 #define EMIFS_CONFIG_ASM_OFFSET		0x0c
48 #define EMIFF_SDRAM_CONFIG_ASM_OFFSET	0x20
55 #define IDLE_WAIT_CYCLES		0x00000fff
56 #define PERIPHERAL_ENABLE		0x2
58 #define SELF_REFRESH_MODE		0x0c000001
59 #define IDLE_EMIFS_REQUEST		0xc
60 #define MODEM_32K_EN			0x1
61 #define PER_EN				0x1
64 #define ULPD_LOW_PWR_EN			0x0001
65 #define ULPD_DEEP_SLEEP_TRANSITION_EN	0x0010
66 #define ULPD_SETUP_ANALOG_CELL_3_VAL	0
67 #define ULPD_POWER_CTRL_REG_VAL		0x0219
70 #define DSP_IDLE			0x0040
71 #define DSP_RST				0x0004
72 #define DSP_ENABLE			0x0002
74 #define DEFAULT_MPUI_CONFIG		0x05cf
75 #define ENABLE_XORCLK			0x2
76 #define DSP_CLOCK_ENABLE		0x2000
77 #define DSP_IDLE_MODE			0x2
78 #define TC_IDLE_REQUEST			(0x0000000c)
80 #define IRQ_LEVEL2			(1<<0)
84 #define PDE_BIT				0x08
85 #define PWD_EN_BIT			0x04
86 #define EN_PERCK_BIT			0x04
88 #define OMAP1510_DEEP_SLEEP_REQUEST	0x0ec7
89 #define OMAP1510_BIG_SLEEP_REQUEST	0x0cc5
90 #define OMAP1510_IDLE_LOOP_REQUEST	0x0c00
91 #define OMAP1510_IDLE_CLOCK_DOMAINS	0x2
94 #define OMAP1610_IDLECT1_SLEEP_VAL	0x13c7
95 #define OMAP1610_IDLECT2_SLEEP_VAL	0x09c7
96 #define OMAP1610_IDLECT3_VAL		0x3f
97 #define OMAP1610_IDLECT3_SLEEP_ORMASK	0x2c
98 #define OMAP1610_IDLECT3		0xfffece24
99 #define OMAP1610_IDLE_LOOP_REQUEST	0x0400
101 #define OMAP7XX_IDLECT1_SLEEP_VAL	0x16c7
102 #define OMAP7XX_IDLECT2_SLEEP_VAL	0x09c7
103 #define OMAP7XX_IDLECT3_VAL		0x3f
104 #define OMAP7XX_IDLECT3		0xfffece24
105 #define OMAP7XX_IDLE_LOOP_REQUEST	0x0C00
178 	ARM_SLEEP_SAVE_START = 0,
194 	DSP_SLEEP_SAVE_START = 0,
203 	ULPD_SLEEP_SAVE_START = 0,
217 	MPUI1510_SLEEP_SAVE_START = 0,
232 	MPUI1510_SLEEP_SAVE_SIZE = 0
237 	MPUI7XX_SLEEP_SAVE_START = 0,
253 	MPUI7XX_SLEEP_SAVE_SIZE = 0
258 	MPUI1610_SLEEP_SAVE_START = 0,
276 	MPUI1610_SLEEP_SAVE_SIZE = 0