Lines Matching +full:4 +full:x2
12 #define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
17 #define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
23 #define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
29 #define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
34 #define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
35 #define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
36 #define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
37 #define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
40 #define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
45 #define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
50 #define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
65 #define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
72 #define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
77 #define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
83 #define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
88 #define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
93 #define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
100 #define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
106 #define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
112 #define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
118 #define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
125 #define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
133 #define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
140 #define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
156 MPP_62_63 = 4,
180 * The MPP[52:57] functionality is encoded by 4 bits in different
185 #define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2