Lines Matching +full:0 +full:- +full:7
12 #include <linux/clk-provider.h>
15 #include <linux/dma-mapping.h>
19 #include <linux/irqchip/irq-davinci-aintc.h>
21 #include <linux/platform_data/gpio-davinci.h>
32 #include <clocksource/timer-davinci.h>
39 #define DAVINCI_VPIF_BASE (0x01C12000)
42 BIT_MASK(0))
46 #define DM646X_EMAC_BASE 0x01c80000
47 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
48 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
49 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
50 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
51 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
64 .end = DM646X_EMAC_BASE + SZ_16K - 1,
102 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
109 .id = 0,
122 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
124 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
126 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
128 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
130 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
132 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
134 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
136 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
138 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
140 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
142 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
144 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
146 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
148 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
153 [IRQ_DM646X_VP_VERTINT0] = 7,
154 [IRQ_DM646X_VP_VERTINT1] = 7,
155 [IRQ_DM646X_VP_VERTINT2] = 7,
156 [IRQ_DM646X_VP_VERTINT3] = 7,
157 [IRQ_DM646X_VP_ERRINT] = 7,
158 [IRQ_DM646X_RESERVED_1] = 7,
159 [IRQ_DM646X_RESERVED_2] = 7,
160 [IRQ_DM646X_WDINT] = 7,
161 [IRQ_DM646X_CRGENINT0] = 7,
162 [IRQ_DM646X_CRGENINT1] = 7,
163 [IRQ_DM646X_TSIFINT0] = 7,
164 [IRQ_DM646X_TSIFINT1] = 7,
165 [IRQ_DM646X_VDCEINT] = 7,
166 [IRQ_DM646X_USBINT] = 7,
167 [IRQ_DM646X_USBDMAINT] = 7,
168 [IRQ_DM646X_PCIINT] = 7,
169 [IRQ_CCINT0] = 7, /* dma */
170 [IRQ_CCERRINT] = 7, /* dma */
171 [IRQ_TCERRINT0] = 7, /* dma */
172 [IRQ_TCERRINT] = 7, /* dma */
173 [IRQ_DM646X_TCERRINT2] = 7,
174 [IRQ_DM646X_TCERRINT3] = 7,
175 [IRQ_DM646X_IDE] = 7,
176 [IRQ_DM646X_HPIINT] = 7,
177 [IRQ_DM646X_EMACRXTHINT] = 7,
178 [IRQ_DM646X_EMACRXINT] = 7,
179 [IRQ_DM646X_EMACTXINT] = 7,
180 [IRQ_DM646X_EMACMISCINT] = 7,
181 [IRQ_DM646X_MCASP0TXINT] = 7,
182 [IRQ_DM646X_MCASP0RXINT] = 7,
183 [IRQ_DM646X_RESERVED_3] = 7,
184 [IRQ_DM646X_MCASP1TXINT] = 7,
185 [IRQ_TINT0_TINT12] = 7, /* clockevent */
186 [IRQ_TINT0_TINT34] = 7, /* clocksource */
187 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
188 [IRQ_TINT1_TINT34] = 7, /* system tick */
189 [IRQ_PWMINT0] = 7,
190 [IRQ_PWMINT1] = 7,
191 [IRQ_DM646X_VLQINT] = 7,
192 [IRQ_I2C] = 7,
193 [IRQ_UARTINT0] = 7,
194 [IRQ_UARTINT1] = 7,
195 [IRQ_DM646X_UARTINT2] = 7,
196 [IRQ_DM646X_SPINT0] = 7,
197 [IRQ_DM646X_SPINT1] = 7,
198 [IRQ_DM646X_DSP2ARMINT] = 7,
199 [IRQ_DM646X_RESERVED_4] = 7,
200 [IRQ_DM646X_PSCINT] = 7,
201 [IRQ_DM646X_GPIO0] = 7,
202 [IRQ_DM646X_GPIO1] = 7,
203 [IRQ_DM646X_GPIO2] = 7,
204 [IRQ_DM646X_GPIO3] = 7,
205 [IRQ_DM646X_GPIO4] = 7,
206 [IRQ_DM646X_GPIO5] = 7,
207 [IRQ_DM646X_GPIO6] = 7,
208 [IRQ_DM646X_GPIO7] = 7,
209 [IRQ_DM646X_GPIOBNK0] = 7,
210 [IRQ_DM646X_GPIOBNK1] = 7,
211 [IRQ_DM646X_GPIOBNK2] = 7,
212 [IRQ_DM646X_DDRINT] = 7,
213 [IRQ_DM646X_AEMIFINT] = 7,
214 [IRQ_COMMTX] = 7,
215 [IRQ_COMMRX] = 7,
216 [IRQ_EMUINT] = 7,
219 /*----------------------------------------------------------------------*/
224 {0, 4},
225 {1, 0},
228 {-1, -1},
232 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
233 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
234 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
235 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
236 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
249 .start = 0x01c00000,
250 .end = 0x01c00000 + SZ_64K - 1,
255 .start = 0x01c10000,
256 .end = 0x01c10000 + SZ_1K - 1,
261 .start = 0x01c10400,
262 .end = 0x01c10400 + SZ_1K - 1,
267 .start = 0x01c10800,
268 .end = 0x01c10800 + SZ_1K - 1,
273 .start = 0x01c10c00,
274 .end = 0x01c10c00 + SZ_1K - 1,
292 .id = 0,
304 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
336 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
353 .name = "davinci-mcasp",
354 .id = 0,
360 .name = "davinci-mcasp",
367 .name = "spdif-dit",
368 .id = -1,
376 .end = DAVINCI_VPIF_BASE + 0x03ff,
383 .id = -1,
407 .id = -1,
431 .id = -1,
443 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
465 .base = 0,
475 /*----------------------------------------------------------------------*/
489 .variant = 0x0,
490 .part_no = 0xb770,
491 .manufacturer = 0x017,
496 .variant = 0x1,
497 .part_no = 0xb770,
498 .manufacturer = 0x017,
526 .flags = 0,
539 .flags = 0,
552 .flags = 0,
585 .jtag_id_reg = 0x01c40028,
592 .sram_dma = 0x10010000,
657 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate); in dm646x_init_time()
658 clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate); in dm646x_init_time()
679 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
685 .name = "dm646x-pll2",
686 .id = -1,
700 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
714 int ret = 0; in dm646x_init_devices()
717 return 0; in dm646x_init_devices()