Lines Matching +full:self +full:- +full:refresh
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
88 * @ena: 0 - disable regulator
89 * 1 - enable regulator
121 * Enable self-refresh
160 /* Switch to self-refresh. */
166 /* Wait for self-refresh enter. */
172 /* Put DDR PHY's DLL in bypass mode for non-backup modes. */
199 * Disable self-refresh
229 /* Enable quasi-dynamic programming. */
233 /* De-assert SDRAM initialization. */
238 /* Quasi-dynamic programming done. */
247 /* DLL soft-reset + DLL lock wait + ITM reset */
258 /* Enable quasi-dynamic programming. */
277 /* Trigger self-refresh exit. */
283 /* Wait for self-refresh exit done. */
314 * Enable self-refresh
328 /* Active SDRAM self-refresh mode */
341 /* LPDDR1 --> force DDR2 mode during self-refresh */
351 /* Active DDRC self-refresh mode */
372 /* Active DDRC self-refresh mode */
386 /* Active SDRAMC self-refresh mode */
400 * Disable self-refresh
419 * For exiting the self-refresh mode, do nothing,
420 * automatically exit the self-refresh mode.
571 /* Switch the main clock source to 12-MHz RC oscillator */
923 * - MAINCK if using ULP0 fast variant
924 * - slow clock, otherwise
1007 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
1011 stmfd sp!, {r4 - r12, lr}
1032 * to RAM may be limited while in self-refresh.
1067 /* Active the self-refresh mode */
1089 /* Exit the self-refresh mode */
1093 ldmfd sp!, {r4 - r12, pc}
1142 .word .-at91_pm_suspend_in_sram