Lines Matching +full:non +full:- +full:pc
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
9 * Low-level vector interface routines
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
23 #include <mach/entry-macro.S>
30 #include <asm/uaccess-asm.h>
32 #include "entry-header.S"
33 #include <asm/entry-macro-multi.S>
44 ldr pc, [r1]
55 mov lr, pc
56 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
65 @ Call the processor-specific abort handler:
67 @ r2 - pt_regs
68 @ r4 - aborted context pc
69 @ r5 - aborted context psr
76 mov lr, pc
77 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
90 ARM( stmib sp, {r1 - lr} )
91 THUMB( stmia sp, {r0 - r12} )
120 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
125 ldmia r0, {r4 - r6}
127 mov r7, #-1 @ "" "" "" ""
129 stmia r0, {r5 - r7} @ lr_<exception>,
148 UNWIND(.save {r0 - pc} )
149 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
159 stmia sp, {r1 - r12}
161 ldmia r0, {r3 - r5}
162 add r7, sp, #S_SP - 4 @ here for interlock avoidance
163 mov r6, #-1 @ "" "" "" ""
164 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
166 str r3, [sp, #-4]! @ save the "real" r0 copied
174 @ r2 - sp_svc
175 @ r3 - lr_svc
176 @ r4 - lr_<exception>, already fixed up for correct return/restart
177 @ r5 - spsr_<exception>
178 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
180 stmia r7, {r2 - r6}
233 @ Correct the PC such that it is pointing at the instruction
235 @ the PC will be pointing at the next instruction, and have to
236 @ subtract 4. Otherwise, it is Thumb, and the PC will be
256 mov r1, #4 @ PC correction to apply
258 THUMB( movne r1, #2 ) @ if so, fix up PC correction
318 stmfd sp!, {r1 - r2}
323 ldmfd sp!, {r1 - r2}
340 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
351 ARM( stmib sp, {r1 - r12} )
352 THUMB( stmia sp, {r0 - r12} )
357 ldmia r0, {r3 - r5}
359 mov r6, #-1 @ "" "" "" ""
369 @ r4 - lr_<exception>, already fixed up for correct return/restart
370 @ r5 - spsr_<exception>
371 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
375 stmia r0, {r4 - r6}
377 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
403 #warning "NPTL on non MMU needs fixing"
446 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
448 @ r3 = regs->ARM_cpsr
463 sub r4, r2, #4 @ ARM instr at LR - 4
469 @ r0 = 32-bit ARM instruction which caused the exception
470 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
471 @ r4 = PC value for the faulting instruction
472 @ lr = 32-bit undefined instruction function
478 sub r4, r2, #2 @ First half of thumb instr at LR - 2
481 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
487 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
507 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
511 @ r0 = the two 16-bit Thumb instructions which caused the exception
512 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
513 @ r4 = PC value for the first 16-bit Thumb instruction
547 * Check whether the instruction is a co-processor instruction.
548 * If yes, we need to call the relevant co-processor handler.
550 * Note that we don't do a full check here for the co-processor
553 * co-processor instructions. However, we have to watch out
557 * NEON instructions are co-processor instructions, so we have
564 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
565 * r2 = PC value to resume execution after successful emulation
572 @ Fall-through from Thumb-2 __und_usr
597 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
612 ARM( add pc, pc, r8, lsr #6 )
614 THUMB( add pc, r8 )
672 ldr pc, [r4] @ Call FP module USR entry point
677 * r2 = PC+4
746 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
747 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
779 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
780 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
782 THUMB( ldr pc, [ip] )
791 * Each segment is 32-byte aligned and will be moved to the top of the high
809 .if (. - \sym) & 3
810 .rept 4 - (. - \sym) & 3
814 .rept (\size - (. - \sym)) / 4
866 ldmfd sp!, {r4, r5, r6, pc}
876 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
878 rsbscs r8, r8, #(2b - 1b)
887 #warning "NPTL on non MMU needs fixing"
888 mov r0, #-1
916 * the IRQ and data abort exception handlers to set the pc back
934 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
936 rsbscs r8, r8, #(2b - 1b)
942 #warning "NPTL on non MMU needs fixing"
943 mov r0, #-1
957 /* beware -- each __kuser slot must be 8 instructions max */
966 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
975 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
992 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
994 * SP points to a minimal amount of processor-private memory, the address
1006 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1027 ARM( ldr lr, [pc, lr, lsl #2] )
1028 movs pc, lr @ branch to handler in SVC mode
1070 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1093 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1116 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1141 *-----------------------------------------------------------------------------
1143 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1151 *-----------------------------------------------------------------------------
1180 W(ldr) pc, .L__vectors_start + 0x1000