Lines Matching +full:mode +full:- +full:reg
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2000 Russell King
10 * Do not include any C declarations in this file - it is included by
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
25 #include <asm/uaccess-asm.h>
56 /* Select code for any configuration running in BE8 mode */
76 * set to write-allocate (this would need further testing on XScale when WA
79 * On Feroceon there is much to gain however, regardless of cache mode.
113 stmdb sp!, {r0-r3, ip, lr}
117 ldmia sp!, {r0-r3, ip, lr}
129 stmdb sp!, {r0-r3, ip, lr}
133 ldmia sp!, {r0-r3, ip, lr}
149 * assumes FIQs are enabled, and that the processor is in SVC mode.
262 .long 9998b - . ;\
264 .if . - 9997b == 2 ;\
267 .if . - 9997b != 4 ;\
273 .long 9998b - . ;\
274 W(b) . + (label - 9998b) ;\
296 .macro smp_dmb mode
299 .ifeqs "\mode","arm"
309 .ifeqs "\mode","arm"
319 * setmode is used to assert to be in svc mode during boot. For v7-M
322 .macro setmode, mode, reg
325 .macro setmode, mode, reg
326 mov \reg, #\mode
327 msr cpsr_c, \reg
330 .macro setmode, mode, reg
331 msr cpsr_c, #\mode
336 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
339 * This macro is intended for forcing the CPU into SVC mode at boot time.
340 * you cannot return to the original mode.
342 .macro safe_svcmode_maskall reg:req
344 mrs \reg , cpsr
345 eor \reg, \reg, #HYP_MODE
346 tst \reg, #MODE_MASK
347 bic \reg , \reg , #MODE_MASK
348 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
349 THUMB( orr \reg , \reg , #PSR_T_BIT )
351 orr \reg, \reg, #PSR_A_BIT
353 msr spsr_cxsf, \reg
356 1: msr cpsr_c, \reg
360 * workaround for possibly broken pre-v6 hardware
361 * (akita, Sharp Zaurus C-1000, PXA270-based)
363 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
368 * STRT/LDRT access macros with ARM and Thumb-2 variants
372 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
375 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
377 \instr\t\cond\().w \reg, [\ptr, #\off]
388 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
402 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
404 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
412 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
416 \instr\()b\t\cond \reg, [\ptr], #\inc
418 \instr\t\cond \reg, [\ptr], #\inc
432 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
433 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
436 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
437 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
445 .size \name , . - \name
449 .macro ret\c, reg
451 mov\c pc, \reg
453 .ifeqs "\reg", "lr"
454 bx\c \reg
456 mov\c pc, \reg
462 .macro ret.w, reg
463 ret \reg
497 .macro __adldst_l, op, reg, sym, tmp, c
502 .La\@: .long \sym - .Lpc\@
508 movw\c \tmp, #:lower16:\sym - .Lpc\@
509 movt\c \tmp, #:upper16:\sym - .Lpc\@
515 add\c \reg, \tmp, pc
517 \op\c \reg, [pc, \tmp]
522 * In Thumb-2 builds, the PC bias depends on whether we are currently
524 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
525 * emitting in ARM mode, so let's use this to account for the bias.
527 .set .Lpc\@, . + (. - .Lb\@)
530 \op\c \reg, [\tmp]
536 * mov_l - move a constant value or [relocated] address into a register
548 * adr_l - adr pseudo-op with unlimited range
559 * ldr_l - ldr <literal> pseudo-op with unlimited range
570 * str_l - str <literal> pseudo-op with unlimited range
582 * rev_l - byte-swap a 32-bit value