Lines Matching +full:zynq +full:- +full:gpio +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <®ulator_vccpint>;
22 operating-points = <
29 cpu1: cpu@1 {
30 compatible = "arm,cortex-a9";
32 reg = <1>;
37 fpga_full: fpga-full {
38 compatible = "fpga-region";
39 fpga-mgr = <&devcfg>;
40 #address-cells = <1>;
41 #size-cells = <1>;
46 compatible = "arm,cortex-a9-pmu";
48 interrupt-parent = <&intc>;
54 compatible = "regulator-fixed";
55 regulator-name = "VCCPINT";
56 regulator-min-microvolt = <1000000>;
57 regulator-max-microvolt = <1000000>;
58 regulator-boot-on;
59 regulator-always-on;
63 compatible = "arm,coresight-static-replicator";
65 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
67 out-ports {
68 #address-cells = <1>;
69 #size-cells = <0>;
75 remote-endpoint = <&tpiu_in_port>;
78 port@1 {
79 reg = <1>;
81 remote-endpoint = <&etb_in_port>;
85 in-ports {
89 remote-endpoint = <&funnel_out_port>;
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 interrupt-parent = <&intc>;
103 compatible = "xlnx,zynq-xadc-1.00.a";
106 interrupt-parent = <&intc>;
111 compatible = "xlnx,zynq-can-1.0";
114 clock-names = "can_clk", "pclk";
117 interrupt-parent = <&intc>;
118 tx-fifo-depth = <0x40>;
119 rx-fifo-depth = <0x40>;
123 compatible = "xlnx,zynq-can-1.0";
126 clock-names = "can_clk", "pclk";
129 interrupt-parent = <&intc>;
130 tx-fifo-depth = <0x40>;
131 rx-fifo-depth = <0x40>;
134 gpio0: gpio@e000a000 {
135 compatible = "xlnx,zynq-gpio-1.0";
136 #gpio-cells = <2>;
138 gpio-controller;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 interrupt-parent = <&intc>;
147 compatible = "cdns,i2c-r1p10";
150 interrupt-parent = <&intc>;
153 #address-cells = <1>;
154 #size-cells = <0>;
158 compatible = "cdns,i2c-r1p10";
161 interrupt-parent = <&intc>;
164 #address-cells = <1>;
165 #size-cells = <0>;
168 intc: interrupt-controller@f8f01000 {
169 compatible = "arm,cortex-a9-gic";
170 #interrupt-cells = <3>;
171 interrupt-controller;
176 L2: cache-controller@f8f02000 {
177 compatible = "arm,pl310-cache";
180 arm,data-latency = <3 2 2>;
181 arm,tag-latency = <2 2 2>;
182 cache-unified;
183 cache-level = <2>;
186 mc: memory-controller@f8006000 {
187 compatible = "xlnx,zynq-ddrc-a05";
192 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
195 clock-names = "uart_clk", "pclk";
201 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
204 clock-names = "uart_clk", "pclk";
210 compatible = "xlnx,zynq-spi-r1p6";
213 interrupt-parent = <&intc>;
216 clock-names = "ref_clk", "pclk";
217 #address-cells = <1>;
218 #size-cells = <0>;
222 compatible = "xlnx,zynq-spi-r1p6";
225 interrupt-parent = <&intc>;
228 clock-names = "ref_clk", "pclk";
229 #address-cells = <1>;
230 #size-cells = <0>;
234 compatible = "cdns,zynq-gem", "cdns,gem";
239 clock-names = "pclk", "hclk", "tx_clk";
240 #address-cells = <1>;
241 #size-cells = <0>;
245 compatible = "cdns,zynq-gem", "cdns,gem";
250 clock-names = "pclk", "hclk", "tx_clk";
251 #address-cells = <1>;
252 #size-cells = <0>;
255 smcc: memory-controller@e000e000 {
256 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
259 clock-names = "memclk", "apb_pclk";
264 #address-cells = <2>;
265 #size-cells = <1>;
267 nfc0: nand-controller@0,0 {
268 compatible = "arm,pl353-nand-r2p1";
271 #address-cells = <1>;
272 #size-cells = <0>;
277 compatible = "arasan,sdhci-8.9a";
279 clock-names = "clk_xin", "clk_ahb";
281 interrupt-parent = <&intc>;
287 compatible = "arasan,sdhci-8.9a";
289 clock-names = "clk_xin", "clk_ahb";
291 interrupt-parent = <&intc>;
297 #address-cells = <1>;
298 #size-cells = <1>;
299 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
303 #clock-cells = <1>;
304 compatible = "xlnx,ps7-clkc";
305 fclk-enable = <0>;
306 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
321 compatible = "xlnx,zynq-reset";
323 #reset-cells = <1>;
328 compatible = "xlnx,pinctrl-zynq";
337 interrupt-parent = <&intc>;
338 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
345 #dma-cells = <1>;
346 #dma-channels = <8>;
347 #dma-requests = <4>;
349 clock-names = "apb_pclk";
353 compatible = "xlnx,zynq-devcfg-1.0";
355 interrupt-parent = <&intc>;
358 clock-names = "ref_clk";
363 compatible = "arm,cortex-a9-global-timer";
365 interrupts = <1 11 0x301>;
366 interrupt-parent = <&intc>;
371 interrupt-parent = <&intc>;
379 interrupt-parent = <&intc>;
387 interrupt-parent = <&intc>;
388 interrupts = <1 13 0x301>;
389 compatible = "arm,cortex-a9-twd-timer";
395 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
398 interrupt-parent = <&intc>;
405 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
408 interrupt-parent = <&intc>;
416 compatible = "cdns,wdt-r1p2";
417 interrupt-parent = <&intc>;
418 interrupts = <0 9 1>;
420 timeout-sec = <10>;
424 compatible = "arm,coresight-etb10", "arm,primecell";
427 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
428 in-ports {
431 remote-endpoint = <&replicator_out_port1>;
438 compatible = "arm,coresight-tpiu", "arm,primecell";
441 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
442 in-ports {
445 remote-endpoint = <&replicator_out_port0>;
452 compatible = "arm,coresight-static-funnel", "arm,primecell";
455 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
458 out-ports {
461 remote-endpoint =
467 in-ports {
468 #address-cells = <1>;
469 #size-cells = <0>;
475 remote-endpoint = <&ptm0_out_port>;
479 port@1 {
480 reg = <1>;
482 remote-endpoint = <&ptm1_out_port>;
496 compatible = "arm,coresight-etm3x", "arm,primecell";
499 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
501 out-ports {
504 remote-endpoint = <&funnel0_in_port0>;
511 compatible = "arm,coresight-etm3x", "arm,primecell";
514 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
516 out-ports {
519 remote-endpoint = <&funnel0_in_port1>;