Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
20 reg = <0x80000000 0x0>;
24 compatible = "nvidia,tegra30-pcie";
26 reg = <0x00003000 0x00000800>, /* PADS registers */
29 reg-names = "pads", "afi", "cs";
32 interrupt-names = "intr", "msi";
34 #interrupt-cells = <1>;
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
39 #address-cells = <3>;
40 #size-cells = <2>;
46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
53 clock-names = "pex", "afi", "pll_e", "cml";
57 reset-names = "pex", "afi", "pcie_x";
62 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
67 #address-cells = <3>;
68 #size-cells = <2>;
71 nvidia,num-lanes = <2>;
76 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
81 #address-cells = <3>;
82 #size-cells = <2>;
85 nvidia,num-lanes = <2>;
90 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
91 reg = <0x001800 0 0 0 0>;
92 bus-range = <0x00 0xff>;
95 #address-cells = <3>;
96 #size-cells = <2>;
99 nvidia,num-lanes = <2>;
104 compatible = "mmio-sram";
105 reg = <0x40000000 0x40000>;
106 #address-cells = <1>;
107 #size-cells = <1>;
111 reg = <0x400 0x3fc00>;
117 compatible = "nvidia,tegra30-host1x";
118 reg = <0x50000000 0x00024000>;
121 interrupt-names = "syncpt", "host1x";
123 clock-names = "host1x";
125 reset-names = "host1x";
128 #address-cells = <1>;
129 #size-cells = <1>;
134 compatible = "nvidia,tegra30-mpe";
135 reg = <0x54040000 0x00040000>;
139 reset-names = "mpe";
145 compatible = "nvidia,tegra30-vi";
146 reg = <0x54080000 0x00040000>;
150 reset-names = "vi";
156 compatible = "nvidia,tegra30-epp";
157 reg = <0x540c0000 0x00040000>;
161 reset-names = "epp";
167 compatible = "nvidia,tegra30-isp";
168 reg = <0x54100000 0x00040000>;
172 reset-names = "isp";
178 compatible = "nvidia,tegra30-gr2d";
179 reg = <0x54140000 0x00040000>;
183 reset-names = "2d";
189 compatible = "nvidia,tegra30-gr3d";
190 reg = <0x54180000 0x00040000>;
193 clock-names = "3d", "3d2";
196 reset-names = "3d", "3d2";
203 compatible = "nvidia,tegra30-dc";
204 reg = <0x54200000 0x00040000>;
208 clock-names = "dc", "parent";
210 reset-names = "dc";
221 interconnect-names = "wina",
223 "winb-vfilter",
233 compatible = "nvidia,tegra30-dc";
234 reg = <0x54240000 0x00040000>;
238 clock-names = "dc", "parent";
240 reset-names = "dc";
251 interconnect-names = "wina",
253 "winb-vfilter",
263 compatible = "nvidia,tegra30-hdmi";
264 reg = <0x54280000 0x00040000>;
268 clock-names = "hdmi", "parent";
270 reset-names = "hdmi";
275 compatible = "nvidia,tegra30-tvo";
276 reg = <0x542c0000 0x00040000>;
283 compatible = "nvidia,tegra30-dsi";
284 reg = <0x54300000 0x00040000>;
287 clock-names = "dsi", "parent";
289 reset-names = "dsi";
294 compatible = "nvidia,tegra30-dsi";
295 reg = <0x54400000 0x00040000>;
298 clock-names = "dsi", "parent";
300 reset-names = "dsi";
306 compatible = "arm,cortex-a9-twd-timer";
307 reg = <0x50040600 0x20>;
308 interrupt-parent = <&intc>;
314 intc: interrupt-controller@50041000 {
315 compatible = "arm,cortex-a9-gic";
316 reg = <0x50041000 0x1000>,
318 interrupt-controller;
319 #interrupt-cells = <3>;
320 interrupt-parent = <&intc>;
323 cache-controller@50043000 {
324 compatible = "arm,pl310-cache";
325 reg = <0x50043000 0x1000>;
326 arm,data-latency = <6 6 2>;
327 arm,tag-latency = <5 5 2>;
328 cache-unified;
329 cache-level = <2>;
332 lic: interrupt-controller@60004000 {
333 compatible = "nvidia,tegra30-ictlr";
334 reg = <0x60004000 0x100>,
339 interrupt-controller;
340 #interrupt-cells = <3>;
341 interrupt-parent = <&intc>;
345 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
346 reg = <0x60005000 0x400>;
357 compatible = "nvidia,tegra30-car";
358 reg = <0x60006000 0x1000>;
359 #clock-cells = <1>;
360 #reset-cells = <1>;
363 flow-controller@60007000 {
364 compatible = "nvidia,tegra30-flowctrl";
365 reg = <0x60007000 0x1000>;
369 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
370 reg = <0x6000a000 0x1400>;
405 reset-names = "dma";
406 #dma-cells = <1>;
410 compatible = "nvidia,tegra30-ahb";
411 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
415 compatible = "nvidia,tegra30-actmon";
416 reg = <0x6000c800 0x400>;
420 clock-names = "actmon", "emc";
422 reset-names = "actmon";
423 operating-points-v2 = <&emc_bw_dfs_opp_table>;
425 interconnect-names = "cpu-read";
426 #cooling-cells = <2>;
430 compatible = "nvidia,tegra30-gpio";
431 reg = <0x6000d000 0x1000>;
440 #gpio-cells = <2>;
441 gpio-controller;
442 #interrupt-cells = <2>;
443 interrupt-controller;
445 gpio-ranges = <&pinmux 0 0 248>;
450 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
451 reg = <0x6001a000 0x1000>, /* Syntax Engine */
454 <0x6001c200 0x100>, /* Post-processing Engine */
460 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
464 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
466 interrupt-names = "sync-token", "bsev", "sxe";
468 reset-names = "vde", "mc";
474 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
475 reg = <0x70000800 0x64>, /* Chip revision */
480 compatible = "nvidia,tegra30-pinmux";
481 reg = <0x70000868 0x0d4>, /* Pad control registers */
489 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
491 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
494 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
495 reg = <0x70006000 0x40>;
496 reg-shift = <2>;
500 reset-names = "serial";
502 dma-names = "rx", "tx";
507 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
508 reg = <0x70006040 0x40>;
509 reg-shift = <2>;
513 reset-names = "serial";
515 dma-names = "rx", "tx";
520 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
521 reg = <0x70006200 0x100>;
522 reg-shift = <2>;
526 reset-names = "serial";
528 dma-names = "rx", "tx";
533 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
534 reg = <0x70006300 0x100>;
535 reg-shift = <2>;
539 reset-names = "serial";
541 dma-names = "rx", "tx";
546 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
547 reg = <0x70006400 0x100>;
548 reg-shift = <2>;
552 reset-names = "serial";
554 dma-names = "rx", "tx";
559 compatible = "nvidia,tegra30-gmi";
560 reg = <0x70009000 0x1000>;
561 #address-cells = <2>;
562 #size-cells = <1>;
565 clock-names = "gmi";
567 reset-names = "gmi";
572 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
573 reg = <0x7000a000 0x100>;
574 #pwm-cells = <2>;
577 reset-names = "pwm";
582 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
583 reg = <0x7000e000 0x100>;
589 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
590 reg = <0x7000c000 0x100>;
592 #address-cells = <1>;
593 #size-cells = <0>;
596 clock-names = "div-clk", "fast-clk";
598 reset-names = "i2c";
600 dma-names = "rx", "tx";
605 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
606 reg = <0x7000c400 0x100>;
608 #address-cells = <1>;
609 #size-cells = <0>;
612 clock-names = "div-clk", "fast-clk";
614 reset-names = "i2c";
616 dma-names = "rx", "tx";
621 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
622 reg = <0x7000c500 0x100>;
624 #address-cells = <1>;
625 #size-cells = <0>;
628 clock-names = "div-clk", "fast-clk";
630 reset-names = "i2c";
632 dma-names = "rx", "tx";
637 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
638 reg = <0x7000c700 0x100>;
640 #address-cells = <1>;
641 #size-cells = <0>;
645 reset-names = "i2c";
646 clock-names = "div-clk", "fast-clk";
648 dma-names = "rx", "tx";
653 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
654 reg = <0x7000d000 0x100>;
656 #address-cells = <1>;
657 #size-cells = <0>;
660 clock-names = "div-clk", "fast-clk";
662 reset-names = "i2c";
664 dma-names = "rx", "tx";
669 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
670 reg = <0x7000d400 0x200>;
672 #address-cells = <1>;
673 #size-cells = <0>;
676 reset-names = "spi";
678 dma-names = "rx", "tx";
683 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
684 reg = <0x7000d600 0x200>;
686 #address-cells = <1>;
687 #size-cells = <0>;
690 reset-names = "spi";
692 dma-names = "rx", "tx";
697 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
698 reg = <0x7000d800 0x200>;
700 #address-cells = <1>;
701 #size-cells = <0>;
704 reset-names = "spi";
706 dma-names = "rx", "tx";
711 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
712 reg = <0x7000da00 0x200>;
714 #address-cells = <1>;
715 #size-cells = <0>;
718 reset-names = "spi";
720 dma-names = "rx", "tx";
725 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
726 reg = <0x7000dc00 0x200>;
728 #address-cells = <1>;
729 #size-cells = <0>;
732 reset-names = "spi";
734 dma-names = "rx", "tx";
739 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
740 reg = <0x7000de00 0x200>;
742 #address-cells = <1>;
743 #size-cells = <0>;
746 reset-names = "spi";
748 dma-names = "rx", "tx";
753 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
754 reg = <0x7000e200 0x100>;
758 reset-names = "kbc";
763 compatible = "nvidia,tegra30-pmc";
764 reg = <0x7000e400 0x400>;
766 clock-names = "pclk", "clk32k_in";
767 #clock-cells = <1>;
770 mc: memory-controller@7000f000 {
771 compatible = "nvidia,tegra30-mc";
772 reg = <0x7000f000 0x400>;
774 clock-names = "mc";
778 #iommu-cells = <1>;
779 #reset-cells = <1>;
780 #interconnect-cells = <1>;
783 emc: memory-controller@7000f400 {
784 compatible = "nvidia,tegra30-emc";
785 reg = <0x7000f400 0x400>;
789 nvidia,memory-controller = <&mc>;
790 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
792 #interconnect-cells = <0>;
796 compatible = "nvidia,tegra30-efuse";
797 reg = <0x7000f800 0x400>;
799 clock-names = "fuse";
801 reset-names = "fuse";
805 compatible = "nvidia,tegra30-tsensor";
806 reg = <0x70014000 0x500>;
811 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
812 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
813 assigned-clock-rates = <500000>;
815 #thermal-sensor-cells = <1>;
819 compatible = "nvidia,tegra30-hda";
820 reg = <0x70030000 0x10000>;
825 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
829 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
834 compatible = "nvidia,tegra30-ahub";
835 reg = <0x70080000 0x200>,
840 clock-names = "d_audio", "apbif";
852 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
859 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
862 #address-cells = <1>;
863 #size-cells = <1>;
866 compatible = "nvidia,tegra30-i2s";
867 reg = <0x70080300 0x100>;
868 nvidia,ahub-cif-ids = <4 4>;
871 reset-names = "i2s";
876 compatible = "nvidia,tegra30-i2s";
877 reg = <0x70080400 0x100>;
878 nvidia,ahub-cif-ids = <5 5>;
881 reset-names = "i2s";
886 compatible = "nvidia,tegra30-i2s";
887 reg = <0x70080500 0x100>;
888 nvidia,ahub-cif-ids = <6 6>;
891 reset-names = "i2s";
896 compatible = "nvidia,tegra30-i2s";
897 reg = <0x70080600 0x100>;
898 nvidia,ahub-cif-ids = <7 7>;
901 reset-names = "i2s";
906 compatible = "nvidia,tegra30-i2s";
907 reg = <0x70080700 0x100>;
908 nvidia,ahub-cif-ids = <8 8>;
911 reset-names = "i2s";
917 compatible = "nvidia,tegra30-sdhci";
918 reg = <0x78000000 0x200>;
921 clock-names = "sdhci";
923 reset-names = "sdhci";
928 compatible = "nvidia,tegra30-sdhci";
929 reg = <0x78000200 0x200>;
932 clock-names = "sdhci";
934 reset-names = "sdhci";
939 compatible = "nvidia,tegra30-sdhci";
940 reg = <0x78000400 0x200>;
943 clock-names = "sdhci";
945 reset-names = "sdhci";
950 compatible = "nvidia,tegra30-sdhci";
951 reg = <0x78000600 0x200>;
954 clock-names = "sdhci";
956 reset-names = "sdhci";
961 compatible = "nvidia,tegra30-ehci", "usb-ehci";
962 reg = <0x7d000000 0x4000>;
967 reset-names = "usb";
968 nvidia,needs-double-reset;
973 phy1: usb-phy@7d000000 {
974 compatible = "nvidia,tegra30-usb-phy";
975 reg = <0x7d000000 0x4000>,
981 clock-names = "reg", "pll_u", "utmi-pads";
983 reset-names = "usb", "utmi-pads";
984 #phy-cells = <0>;
985 nvidia,hssync-start-delay = <9>;
986 nvidia,idle-wait-delay = <17>;
987 nvidia,elastic-limit = <16>;
988 nvidia,term-range-adj = <6>;
989 nvidia,xcvr-setup = <51>;
990 nvidia,xcvr-setup-use-fuses;
991 nvidia,xcvr-lsfslew = <1>;
992 nvidia,xcvr-lsrslew = <1>;
993 nvidia,xcvr-hsslew = <32>;
994 nvidia,hssquelch-level = <2>;
995 nvidia,hsdiscon-level = <5>;
996 nvidia,has-utmi-pad-registers;
1001 compatible = "nvidia,tegra30-ehci", "usb-ehci";
1002 reg = <0x7d004000 0x4000>;
1007 reset-names = "usb";
1012 phy2: usb-phy@7d004000 {
1013 compatible = "nvidia,tegra30-usb-phy";
1014 reg = <0x7d004000 0x4000>,
1020 clock-names = "reg", "pll_u", "utmi-pads";
1022 reset-names = "usb", "utmi-pads";
1023 #phy-cells = <0>;
1024 nvidia,hssync-start-delay = <9>;
1025 nvidia,idle-wait-delay = <17>;
1026 nvidia,elastic-limit = <16>;
1027 nvidia,term-range-adj = <6>;
1028 nvidia,xcvr-setup = <51>;
1029 nvidia,xcvr-setup-use-fuses;
1030 nvidia,xcvr-lsfslew = <2>;
1031 nvidia,xcvr-lsrslew = <2>;
1032 nvidia,xcvr-hsslew = <32>;
1033 nvidia,hssquelch-level = <2>;
1034 nvidia,hsdiscon-level = <5>;
1039 compatible = "nvidia,tegra30-ehci", "usb-ehci";
1040 reg = <0x7d008000 0x4000>;
1045 reset-names = "usb";
1050 phy3: usb-phy@7d008000 {
1051 compatible = "nvidia,tegra30-usb-phy";
1052 reg = <0x7d008000 0x4000>,
1058 clock-names = "reg", "pll_u", "utmi-pads";
1060 reset-names = "usb", "utmi-pads";
1061 #phy-cells = <0>;
1062 nvidia,hssync-start-delay = <0>;
1063 nvidia,idle-wait-delay = <17>;
1064 nvidia,elastic-limit = <16>;
1065 nvidia,term-range-adj = <6>;
1066 nvidia,xcvr-setup = <51>;
1067 nvidia,xcvr-setup-use-fuses;
1068 nvidia,xcvr-lsfslew = <2>;
1069 nvidia,xcvr-lsrslew = <2>;
1070 nvidia,xcvr-hsslew = <32>;
1071 nvidia,hssquelch-level = <2>;
1072 nvidia,hsdiscon-level = <5>;
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1082 compatible = "arm,cortex-a9";
1083 reg = <0>;
1085 #cooling-cells = <2>;
1090 compatible = "arm,cortex-a9";
1091 reg = <1>;
1093 #cooling-cells = <2>;
1098 compatible = "arm,cortex-a9";
1099 reg = <2>;
1101 #cooling-cells = <2>;
1106 compatible = "arm,cortex-a9";
1107 reg = <3>;
1109 #cooling-cells = <2>;
1114 compatible = "arm,cortex-a9-pmu";
1119 interrupt-affinity = <&{/cpus/cpu@0}>,
1125 thermal-zones {
1126 tsensor0-thermal {
1127 polling-delay-passive = <1000>; /* milliseconds */
1128 polling-delay = <5000>; /* milliseconds */
1130 thermal-sensors = <&tsensor 0>;
1133 level1_trip: dvfs-alert {
1140 level2_trip: cpu-div2-throttle {
1147 level3_trip: soc-critical {
1155 cooling-maps {
1158 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1167 tsensor1-thermal {
1170 polling-delay-passive = <1000>; /* milliseconds */
1171 polling-delay = <0>; /* milliseconds */
1173 thermal-sensors = <&tsensor 1>;
1176 dvfs-alert {