Lines Matching +full:0 +full:x6000c800
20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
45 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
47 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
60 pci@1,0 {
62 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
74 pci@2,0 {
76 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
88 pci@3,0 {
90 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
91 reg = <0x001800 0 0 0 0>;
92 bus-range = <0x00 0xff>;
105 reg = <0x40000000 0x40000>;
108 ranges = <0 0x40000000 0x40000>;
111 reg = <0x400 0x3fc00>;
118 reg = <0x50000000 0x00024000>;
131 ranges = <0x54000000 0x54000000 0x04000000>;
135 reg = <0x54040000 0x00040000>;
146 reg = <0x54080000 0x00040000>;
157 reg = <0x540c0000 0x00040000>;
168 reg = <0x54100000 0x00040000>;
179 reg = <0x54140000 0x00040000>;
190 reg = <0x54180000 0x00040000>;
204 reg = <0x54200000 0x00040000>;
214 nvidia,head = <0>;
234 reg = <0x54240000 0x00040000>;
264 reg = <0x54280000 0x00040000>;
276 reg = <0x542c0000 0x00040000>;
284 reg = <0x54300000 0x00040000>;
295 reg = <0x54400000 0x00040000>;
307 reg = <0x50040600 0x20>;
316 reg = <0x50041000 0x1000>,
317 <0x50040100 0x0100>;
325 reg = <0x50043000 0x1000>;
334 reg = <0x60004000 0x100>,
335 <0x60004100 0x50>,
336 <0x60004200 0x50>,
337 <0x60004300 0x50>,
338 <0x60004400 0x50>;
346 reg = <0x60005000 0x400>;
347 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
358 reg = <0x60006000 0x1000>;
365 reg = <0x60007000 0x1000>;
370 reg = <0x6000a000 0x1400>;
411 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
416 reg = <0x6000c800 0x400>;
431 reg = <0x6000d000 0x1000>;
445 gpio-ranges = <&pinmux 0 0 248>;
451 reg = <0x6001a000 0x1000>, /* Syntax Engine */
452 <0x6001b000 0x1000>, /* Video Bitstream Engine */
453 <0x6001c000 0x100>, /* Macroblock Engine */
454 <0x6001c200 0x100>, /* Post-processing Engine */
455 <0x6001c400 0x100>, /* Motion Compensation Engine */
456 <0x6001c600 0x100>, /* Transform Engine */
457 <0x6001c800 0x100>, /* Pixel prediction block */
458 <0x6001ca00 0x100>, /* Video DMA */
459 <0x6001d800 0x400>; /* Video frame controls */
475 reg = <0x70000800 0x64>, /* Chip revision */
476 <0x70000008 0x04>; /* Strapping options */
481 reg = <0x70000868 0x0d4>, /* Pad control registers */
482 <0x70003000 0x3e4>; /* Mux registers */
495 reg = <0x70006000 0x40>;
508 reg = <0x70006040 0x40>;
521 reg = <0x70006200 0x100>;
534 reg = <0x70006300 0x100>;
547 reg = <0x70006400 0x100>;
560 reg = <0x70009000 0x1000>;
563 ranges = <0 0 0x48000000 0x7ffffff>;
573 reg = <0x7000a000 0x100>;
583 reg = <0x7000e000 0x100>;
590 reg = <0x7000c000 0x100>;
593 #size-cells = <0>;
606 reg = <0x7000c400 0x100>;
609 #size-cells = <0>;
622 reg = <0x7000c500 0x100>;
625 #size-cells = <0>;
638 reg = <0x7000c700 0x100>;
641 #size-cells = <0>;
654 reg = <0x7000d000 0x100>;
657 #size-cells = <0>;
670 reg = <0x7000d400 0x200>;
673 #size-cells = <0>;
684 reg = <0x7000d600 0x200>;
687 #size-cells = <0>;
698 reg = <0x7000d800 0x200>;
701 #size-cells = <0>;
712 reg = <0x7000da00 0x200>;
715 #size-cells = <0>;
726 reg = <0x7000dc00 0x200>;
729 #size-cells = <0>;
740 reg = <0x7000de00 0x200>;
743 #size-cells = <0>;
754 reg = <0x7000e200 0x100>;
764 reg = <0x7000e400 0x400>;
772 reg = <0x7000f000 0x400>;
785 reg = <0x7000f400 0x400>;
792 #interconnect-cells = <0>;
797 reg = <0x7000f800 0x400>;
806 reg = <0x70014000 0x500>;
820 reg = <0x70030000 0x10000>;
835 reg = <0x70080000 0x200>,
836 <0x70080200 0x100>;
867 reg = <0x70080300 0x100>;
877 reg = <0x70080400 0x100>;
887 reg = <0x70080500 0x100>;
897 reg = <0x70080600 0x100>;
907 reg = <0x70080700 0x100>;
918 reg = <0x78000000 0x200>;
929 reg = <0x78000200 0x200>;
940 reg = <0x78000400 0x200>;
951 reg = <0x78000600 0x200>;
962 reg = <0x7d000000 0x4000>;
975 reg = <0x7d000000 0x4000>,
976 <0x7d000000 0x4000>;
984 #phy-cells = <0>;
1002 reg = <0x7d004000 0x4000>;
1014 reg = <0x7d004000 0x4000>,
1015 <0x7d000000 0x4000>;
1023 #phy-cells = <0>;
1040 reg = <0x7d008000 0x4000>;
1052 reg = <0x7d008000 0x4000>,
1053 <0x7d000000 0x4000>;
1061 #phy-cells = <0>;
1062 nvidia,hssync-start-delay = <0>;
1078 #size-cells = <0>;
1080 cpu0: cpu@0 {
1083 reg = <0>;
1119 interrupt-affinity = <&{/cpus/cpu@0}>,
1130 thermal-sensors = <&tsensor 0>;
1171 polling-delay = <0>; /* milliseconds */