Lines Matching +full:reset +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
13 interrupt-parent = <&lic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
23 compatible = "mmio-sram";
25 #address-cells = <1>;
26 #size-cells = <1>;
36 compatible = "nvidia,tegra20-host1x";
40 interrupt-names = "syncpt", "host1x";
42 clock-names = "host1x";
44 reset-names = "host1x";
46 #address-cells = <1>;
47 #size-cells = <1>;
52 compatible = "nvidia,tegra20-mpe";
57 reset-names = "mpe";
61 compatible = "nvidia,tegra20-vi";
66 reset-names = "vi";
70 compatible = "nvidia,tegra20-epp";
75 reset-names = "epp";
79 compatible = "nvidia,tegra20-isp";
84 reset-names = "isp";
88 compatible = "nvidia,tegra20-gr2d";
93 reset-names = "2d";
97 compatible = "nvidia,tegra20-gr3d";
101 reset-names = "3d";
105 compatible = "nvidia,tegra20-dc";
110 clock-names = "dc", "parent";
112 reset-names = "dc";
121 interconnect-names = "wina",
123 "winb-vfilter",
133 compatible = "nvidia,tegra20-dc";
138 clock-names = "dc", "parent";
140 reset-names = "dc";
149 interconnect-names = "wina",
151 "winb-vfilter",
161 compatible = "nvidia,tegra20-hdmi";
166 clock-names = "hdmi", "parent";
168 reset-names = "hdmi";
173 compatible = "nvidia,tegra20-tvo";
181 compatible = "nvidia,tegra20-dsi";
185 clock-names = "dsi", "parent";
187 reset-names = "dsi";
193 compatible = "arm,cortex-a9-twd-timer";
194 interrupt-parent = <&intc>;
201 intc: interrupt-controller@50041000 {
202 compatible = "arm,cortex-a9-gic";
205 interrupt-controller;
206 #interrupt-cells = <3>;
207 interrupt-parent = <&intc>;
210 cache-controller@50043000 {
211 compatible = "arm,pl310-cache";
213 arm,data-latency = <5 5 2>;
214 arm,tag-latency = <4 4 2>;
215 cache-unified;
216 cache-level = <2>;
219 lic: interrupt-controller@60004000 {
220 compatible = "nvidia,tegra20-ictlr";
225 interrupt-controller;
226 #interrupt-cells = <3>;
227 interrupt-parent = <&intc>;
231 compatible = "nvidia,tegra20-timer";
241 compatible = "nvidia,tegra20-car";
243 #clock-cells = <1>;
244 #reset-cells = <1>;
247 flow-controller@60007000 {
248 compatible = "nvidia,tegra20-flowctrl";
253 compatible = "nvidia,tegra20-apbdma";
273 reset-names = "dma";
274 #dma-cells = <1>;
278 compatible = "nvidia,tegra20-ahb";
283 compatible = "nvidia,tegra20-gpio";
292 #gpio-cells = <2>;
293 gpio-controller;
294 #interrupt-cells = <2>;
295 interrupt-controller;
297 gpio-ranges = <&pinmux 0 0 224>;
302 compatible = "nvidia,tegra20-vde";
306 <0x6001c200 0x100>, /* Post-processing Engine */
312 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
316 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
318 interrupt-names = "sync-token", "bsev", "sxe";
320 reset-names = "vde", "mc";
325 compatible = "nvidia,tegra20-apbmisc";
331 compatible = "nvidia,tegra20-pinmux";
332 reg = <0x70000014 0x10>, /* Tri-state registers */
334 <0x700000a0 0x14>, /* Pull-up/down registers */
339 compatible = "nvidia,tegra20-das";
344 compatible = "nvidia,tegra20-ac97";
349 reset-names = "ac97";
351 dma-names = "rx", "tx";
356 compatible = "nvidia,tegra20-i2s";
361 reset-names = "i2s";
363 dma-names = "rx", "tx";
368 compatible = "nvidia,tegra20-i2s";
373 reset-names = "i2s";
375 dma-names = "rx", "tx";
383 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
384 * driver, the compatible is "nvidia,tegra20-hsuart".
387 compatible = "nvidia,tegra20-uart";
389 reg-shift = <2>;
393 reset-names = "serial";
395 dma-names = "rx", "tx";
400 compatible = "nvidia,tegra20-uart";
402 reg-shift = <2>;
406 reset-names = "serial";
408 dma-names = "rx", "tx";
413 compatible = "nvidia,tegra20-uart";
415 reg-shift = <2>;
419 reset-names = "serial";
421 dma-names = "rx", "tx";
426 compatible = "nvidia,tegra20-uart";
428 reg-shift = <2>;
432 reset-names = "serial";
434 dma-names = "rx", "tx";
439 compatible = "nvidia,tegra20-uart";
441 reg-shift = <2>;
445 reset-names = "serial";
447 dma-names = "rx", "tx";
451 nand-controller@70008000 {
452 compatible = "nvidia,tegra20-nand";
454 #address-cells = <1>;
455 #size-cells = <0>;
458 clock-names = "nand";
460 reset-names = "nand";
461 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
462 assigned-clock-rates = <150000000>;
467 compatible = "nvidia,tegra20-gmi";
469 #address-cells = <2>;
470 #size-cells = <1>;
473 clock-names = "gmi";
475 reset-names = "gmi";
480 compatible = "nvidia,tegra20-pwm";
482 #pwm-cells = <2>;
485 reset-names = "pwm";
490 compatible = "nvidia,tegra20-rtc";
497 compatible = "nvidia,tegra20-i2c";
500 #address-cells = <1>;
501 #size-cells = <0>;
504 clock-names = "div-clk", "fast-clk";
506 reset-names = "i2c";
508 dma-names = "rx", "tx";
513 compatible = "nvidia,tegra20-sflash";
516 #address-cells = <1>;
517 #size-cells = <0>;
520 reset-names = "spi";
522 dma-names = "rx", "tx";
527 compatible = "nvidia,tegra20-i2c";
530 #address-cells = <1>;
531 #size-cells = <0>;
534 clock-names = "div-clk", "fast-clk";
536 reset-names = "i2c";
538 dma-names = "rx", "tx";
543 compatible = "nvidia,tegra20-i2c";
546 #address-cells = <1>;
547 #size-cells = <0>;
550 clock-names = "div-clk", "fast-clk";
552 reset-names = "i2c";
554 dma-names = "rx", "tx";
559 compatible = "nvidia,tegra20-i2c-dvc";
562 #address-cells = <1>;
563 #size-cells = <0>;
566 clock-names = "div-clk", "fast-clk";
568 reset-names = "i2c";
570 dma-names = "rx", "tx";
575 compatible = "nvidia,tegra20-slink";
578 #address-cells = <1>;
579 #size-cells = <0>;
582 reset-names = "spi";
584 dma-names = "rx", "tx";
589 compatible = "nvidia,tegra20-slink";
592 #address-cells = <1>;
593 #size-cells = <0>;
596 reset-names = "spi";
598 dma-names = "rx", "tx";
603 compatible = "nvidia,tegra20-slink";
606 #address-cells = <1>;
607 #size-cells = <0>;
610 reset-names = "spi";
612 dma-names = "rx", "tx";
617 compatible = "nvidia,tegra20-slink";
620 #address-cells = <1>;
621 #size-cells = <0>;
624 reset-names = "spi";
626 dma-names = "rx", "tx";
631 compatible = "nvidia,tegra20-kbc";
636 reset-names = "kbc";
641 compatible = "nvidia,tegra20-pmc";
644 clock-names = "pclk", "clk32k_in";
645 #clock-cells = <1>;
648 mc: memory-controller@7000f000 {
649 compatible = "nvidia,tegra20-mc-gart";
653 clock-names = "mc";
655 #reset-cells = <1>;
656 #iommu-cells = <0>;
657 #interconnect-cells = <1>;
660 emc: memory-controller@7000f400 {
661 compatible = "nvidia,tegra20-emc";
665 #address-cells = <1>;
666 #size-cells = <0>;
667 #interconnect-cells = <0>;
669 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
670 nvidia,memory-controller = <&mc>;
674 compatible = "nvidia,tegra20-efuse";
677 clock-names = "fuse";
679 reset-names = "fuse";
683 compatible = "nvidia,tegra20-pcie";
688 reg-names = "pads", "afi", "cs";
691 interrupt-names = "intr", "msi";
693 #interrupt-cells = <1>;
694 interrupt-map-mask = <0 0 0 0>;
695 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
697 bus-range = <0x00 0xff>;
698 #address-cells = <3>;
699 #size-cells = <2>;
704 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
710 clock-names = "pex", "afi", "pll_e";
714 reset-names = "pex", "afi", "pcie_x";
719 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
721 bus-range = <0x00 0xff>;
724 #address-cells = <3>;
725 #size-cells = <2>;
728 nvidia,num-lanes = <2>;
733 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
735 bus-range = <0x00 0xff>;
738 #address-cells = <3>;
739 #size-cells = <2>;
742 nvidia,num-lanes = <2>;
747 compatible = "nvidia,tegra20-ehci", "usb-ehci";
751 nvidia,has-legacy-mode;
754 reset-names = "usb";
755 nvidia,needs-double-reset;
760 phy1: usb-phy@c5000000 {
761 compatible = "nvidia,tegra20-usb-phy";
769 clock-names = "reg", "pll_u", "timer", "utmi-pads";
771 reset-names = "usb", "utmi-pads";
772 #phy-cells = <0>;
773 nvidia,has-legacy-mode;
774 nvidia,hssync-start-delay = <9>;
775 nvidia,idle-wait-delay = <17>;
776 nvidia,elastic-limit = <16>;
777 nvidia,term-range-adj = <6>;
778 nvidia,xcvr-setup = <9>;
779 nvidia,xcvr-lsfslew = <1>;
780 nvidia,xcvr-lsrslew = <1>;
781 nvidia,has-utmi-pad-registers;
786 compatible = "nvidia,tegra20-ehci", "usb-ehci";
792 reset-names = "usb";
797 phy2: usb-phy@c5004000 {
798 compatible = "nvidia,tegra20-usb-phy";
804 clock-names = "reg", "pll_u", "ulpi-link";
806 reset-names = "usb", "utmi-pads";
807 #phy-cells = <0>;
812 compatible = "nvidia,tegra20-ehci", "usb-ehci";
818 reset-names = "usb";
823 phy3: usb-phy@c5008000 {
824 compatible = "nvidia,tegra20-usb-phy";
832 clock-names = "reg", "pll_u", "timer", "utmi-pads";
834 reset-names = "usb", "utmi-pads";
835 #phy-cells = <0>;
836 nvidia,hssync-start-delay = <9>;
837 nvidia,idle-wait-delay = <17>;
838 nvidia,elastic-limit = <16>;
839 nvidia,term-range-adj = <6>;
840 nvidia,xcvr-setup = <9>;
841 nvidia,xcvr-lsfslew = <2>;
842 nvidia,xcvr-lsrslew = <2>;
847 compatible = "nvidia,tegra20-sdhci";
851 clock-names = "sdhci";
853 reset-names = "sdhci";
858 compatible = "nvidia,tegra20-sdhci";
862 clock-names = "sdhci";
864 reset-names = "sdhci";
869 compatible = "nvidia,tegra20-sdhci";
873 clock-names = "sdhci";
875 reset-names = "sdhci";
880 compatible = "nvidia,tegra20-sdhci";
884 clock-names = "sdhci";
886 reset-names = "sdhci";
891 #address-cells = <1>;
892 #size-cells = <0>;
896 compatible = "arm,cortex-a9";
903 compatible = "arm,cortex-a9";
910 compatible = "arm,cortex-a9-pmu";
913 interrupt-affinity = <&{/cpus/cpu@0}>,