Lines Matching +full:0 +full:x7000f400
17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
49 ranges = <0x54000000 0x54000000 0x04000000>;
53 reg = <0x54040000 0x00040000>;
62 reg = <0x54080000 0x00040000>;
71 reg = <0x540c0000 0x00040000>;
80 reg = <0x54100000 0x00040000>;
89 reg = <0x54140000 0x00040000>;
98 reg = <0x54180000 0x00040000>;
106 reg = <0x54200000 0x00040000>;
114 nvidia,head = <0>;
134 reg = <0x54240000 0x00040000>;
162 reg = <0x54280000 0x00040000>;
174 reg = <0x542c0000 0x00040000>;
182 reg = <0x54300000 0x00040000>;
195 reg = <0x50040600 0x20>;
203 reg = <0x50041000 0x1000>,
204 <0x50040100 0x0100>;
212 reg = <0x50043000 0x1000>;
221 reg = <0x60004000 0x100>,
222 <0x60004100 0x50>,
223 <0x60004200 0x50>,
224 <0x60004300 0x50>;
232 reg = <0x60005000 0x60>;
233 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
242 reg = <0x60006000 0x1000>;
249 reg = <0x60007000 0x1000>;
254 reg = <0x6000a000 0x1200>;
279 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
284 reg = <0x6000d000 0x1000>;
297 gpio-ranges = <&pinmux 0 0 224>;
303 reg = <0x6001a000 0x1000>, /* Syntax Engine */
304 <0x6001b000 0x1000>, /* Video Bitstream Engine */
305 <0x6001c000 0x100>, /* Macroblock Engine */
306 <0x6001c200 0x100>, /* Post-processing Engine */
307 <0x6001c400 0x100>, /* Motion Compensation Engine */
308 <0x6001c600 0x100>, /* Transform Engine */
309 <0x6001c800 0x100>, /* Pixel prediction block */
310 <0x6001ca00 0x100>, /* Video DMA */
311 <0x6001d800 0x300>; /* Video frame controls */
326 reg = <0x70000800 0x64>, /* Chip revision */
327 <0x70000008 0x04>; /* Strapping options */
332 reg = <0x70000014 0x10>, /* Tri-state registers */
333 <0x70000080 0x20>, /* Mux registers */
334 <0x700000a0 0x14>, /* Pull-up/down registers */
335 <0x70000868 0xa8>; /* Pad control registers */
340 reg = <0x70000c00 0x80>;
345 reg = <0x70002000 0x200>;
357 reg = <0x70002800 0x200>;
369 reg = <0x70002a00 0x200>;
388 reg = <0x70006000 0x40>;
401 reg = <0x70006040 0x40>;
414 reg = <0x70006200 0x100>;
427 reg = <0x70006300 0x100>;
440 reg = <0x70006400 0x100>;
453 reg = <0x70008000 0x100>;
455 #size-cells = <0>;
468 reg = <0x70009000 0x1000>;
471 ranges = <0 0 0xd0000000 0xfffffff>;
481 reg = <0x7000a000 0x100>;
491 reg = <0x7000e000 0x100>;
498 reg = <0x7000c000 0x100>;
501 #size-cells = <0>;
514 reg = <0x7000c380 0x80>;
517 #size-cells = <0>;
528 reg = <0x7000c400 0x100>;
531 #size-cells = <0>;
544 reg = <0x7000c500 0x100>;
547 #size-cells = <0>;
560 reg = <0x7000d000 0x200>;
563 #size-cells = <0>;
576 reg = <0x7000d400 0x200>;
579 #size-cells = <0>;
590 reg = <0x7000d600 0x200>;
593 #size-cells = <0>;
604 reg = <0x7000d800 0x200>;
607 #size-cells = <0>;
618 reg = <0x7000da00 0x200>;
621 #size-cells = <0>;
632 reg = <0x7000e200 0x100>;
642 reg = <0x7000e400 0x400>;
650 reg = <0x7000f000 0x00000400>, /* controller registers */
651 <0x58000000 0x02000000>; /* GART aperture */
656 #iommu-cells = <0>;
662 reg = <0x7000f400 0x400>;
666 #size-cells = <0>;
667 #interconnect-cells = <0>;
675 reg = <0x7000f800 0x400>;
685 reg = <0x80003000 0x00000800>, /* PADS registers */
686 <0x80003800 0x00000200>, /* AFI registers */
687 <0x90000000 0x10000000>; /* configuration space */
694 interrupt-map-mask = <0 0 0 0>;
695 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
697 bus-range = <0x00 0xff>;
701 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
702 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
703 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
704 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
705 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
717 pci@1,0 {
719 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
720 reg = <0x000800 0 0 0 0>;
721 bus-range = <0x00 0xff>;
731 pci@2,0 {
733 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
734 reg = <0x001000 0 0 0 0>;
735 bus-range = <0x00 0xff>;
748 reg = <0xc5000000 0x4000>;
762 reg = <0xc5000000 0x4000>,
763 <0xc5000000 0x4000>;
772 #phy-cells = <0>;
787 reg = <0xc5004000 0x4000>;
799 reg = <0xc5004000 0x4000>;
807 #phy-cells = <0>;
813 reg = <0xc5008000 0x4000>;
825 reg = <0xc5008000 0x4000>,
826 <0xc5000000 0x4000>;
835 #phy-cells = <0>;
848 reg = <0xc8000000 0x200>;
859 reg = <0xc8000200 0x200>;
870 reg = <0xc8000400 0x200>;
881 reg = <0xc8000600 0x200>;
892 #size-cells = <0>;
894 cpu@0 {
897 reg = <0>;
913 interrupt-affinity = <&{/cpus/cpu@0}>,