Lines Matching +full:0 +full:x6000c800
21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
60 pci@1,0 {
62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
74 pci@2,0 {
76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
91 reg = <0x0 0x50000000 0x0 0x00034000>;
104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
108 reg = <0x0 0x54200000 0x0 0x00040000>;
117 nvidia,head = <0>;
135 reg = <0x0 0x54240000 0x0 0x00040000>;
158 reg = <0x0 0x54280000 0x0 0x00040000>;
170 reg = <0x0 0x54340000 0x0 0x00040000>;
182 reg = <0x0 0x54540000 0x0 0x00040000>;
197 reg = <0x0 0x545c0000 0x0 0x00040000>;
208 #size-cells = <0>;
217 reg = <0x0 0x50041000 0x0 0x1000>,
218 <0x0 0x50042000 0x0 0x1000>,
219 <0x0 0x50044000 0x0 0x2000>,
220 <0x0 0x50046000 0x0 0x2000>;
227 * Please keep the following 0, notation in place as a former mainline
231 gpu@0,57000000 {
233 reg = <0x0 0x57000000 0x0 0x01000000>,
234 <0x0 0x58000000 0x0 0x01000000>;
251 reg = <0x0 0x60004000 0x0 0x100>,
252 <0x0 0x60004100 0x0 0x100>,
253 <0x0 0x60004200 0x0 0x100>,
254 <0x0 0x60004300 0x0 0x100>,
255 <0x0 0x60004400 0x0 0x100>;
263 reg = <0x0 0x60005000 0x0 0x400>;
264 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
275 reg = <0x0 0x60006000 0x0 0x1000>;
283 reg = <0x0 0x60007000 0x0 0x1000>;
288 reg = <0x0 0x6000c800 0x0 0x400>;
303 reg = <0x0 0x6000d000 0x0 0x1000>;
317 gpio-ranges = <&pinmux 0 0 251>;
323 reg = <0x0 0x60020000 0x0 0x1400>;
364 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
365 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
370 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
371 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
372 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
385 reg = <0x0 0x70006000 0x0 0x40>;
398 reg = <0x0 0x70006040 0x0 0x40>;
411 reg = <0x0 0x70006200 0x0 0x40>;
424 reg = <0x0 0x70006300 0x0 0x40>;
437 reg = <0x0 0x7000a000 0x0 0x100>;
447 reg = <0x0 0x7000c000 0x0 0x100>;
450 #size-cells = <0>;
462 reg = <0x0 0x7000c400 0x0 0x100>;
465 #size-cells = <0>;
477 reg = <0x0 0x7000c500 0x0 0x100>;
480 #size-cells = <0>;
492 reg = <0x0 0x7000c700 0x0 0x100>;
495 #size-cells = <0>;
507 reg = <0x0 0x7000d000 0x0 0x100>;
510 #size-cells = <0>;
522 reg = <0x0 0x7000d100 0x0 0x100>;
525 #size-cells = <0>;
537 reg = <0x0 0x7000d400 0x0 0x200>;
540 #size-cells = <0>;
552 reg = <0x0 0x7000d600 0x0 0x200>;
555 #size-cells = <0>;
567 reg = <0x0 0x7000d800 0x0 0x200>;
570 #size-cells = <0>;
582 reg = <0x0 0x7000da00 0x0 0x200>;
585 #size-cells = <0>;
597 reg = <0x0 0x7000dc00 0x0 0x200>;
600 #size-cells = <0>;
612 reg = <0x0 0x7000de00 0x0 0x200>;
615 #size-cells = <0>;
627 reg = <0x0 0x7000e000 0x0 0x100>;
634 reg = <0x0 0x7000e400 0x0 0x400>;
642 reg = <0x0 0x7000f800 0x0 0x400>;
651 reg = <0x0 0x70019000 0x0 0x1000>;
664 reg = <0x0 0x7001b000 0x0 0x1000>;
671 #interconnect-cells = <0>;
676 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
677 <0x0 0x70020000 0x0 0x7000>; /* SATA */
693 reg = <0x0 0x70030000 0x0 0x10000>;
708 reg = <0x0 0x70090000 0x0 0x8000>,
709 <0x0 0x70098000 0x0 0x1000>,
710 <0x0 0x70099000 0x0 0x1000>;
743 reg = <0x0 0x7009f000 0x0 0x1000>;
752 usb2-0 {
754 #phy-cells = <0>;
759 #phy-cells = <0>;
764 #phy-cells = <0>;
773 ulpi-0 {
775 #phy-cells = <0>;
784 hsic-0 {
786 #phy-cells = <0>;
791 #phy-cells = <0>;
800 pcie-0 {
802 #phy-cells = <0>;
807 #phy-cells = <0>;
812 #phy-cells = <0>;
817 #phy-cells = <0>;
822 #phy-cells = <0>;
831 sata-0 {
833 #phy-cells = <0>;
840 usb2-0 {
852 ulpi-0 {
856 hsic-0 {
864 usb3-0 {
876 reg = <0x0 0x700b0000 0x0 0x200>;
887 reg = <0x0 0x700b0200 0x0 0x200>;
898 reg = <0x0 0x700b0400 0x0 0x200>;
909 reg = <0x0 0x700b0600 0x0 0x200>;
920 reg = <0x0 0x70015000 0x0 0x00001000>;
930 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
931 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
956 reg = <0 0x70110000 0 0x100>, /* DFLL control */
957 <0 0x70110000 0 0x100>, /* I2C output control */
958 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
959 <0 0x70110200 0 0x100>; /* Look-up table RAM */
967 #clock-cells = <0>;
970 nvidia,droop-ctrl = <0x00000f00>;
973 nvidia,ci = <0>;
980 reg = <0x0 0x70300000 0x0 0x200>,
981 <0x0 0x70300800 0x0 0x800>,
982 <0x0 0x70300200 0x0 0x600>;
1032 reg = <0x0 0x70301000 0x0 0x100>;
1042 reg = <0x0 0x70301100 0x0 0x100>;
1052 reg = <0x0 0x70301200 0x0 0x100>;
1062 reg = <0x0 0x70301300 0x0 0x100>;
1072 reg = <0x0 0x70301400 0x0 0x100>;
1083 reg = <0x0 0x7d000000 0x0 0x4000>;
1095 reg = <0x0 0x7d000000 0x0 0x4000>,
1096 <0x0 0x7d000000 0x0 0x4000>;
1104 #phy-cells = <0>;
1105 nvidia,hssync-start-delay = <0>;
1110 nvidia,xcvr-lsfslew = <0>;
1121 reg = <0x0 0x7d004000 0x0 0x4000>;
1133 reg = <0x0 0x7d004000 0x0 0x4000>,
1134 <0x0 0x7d000000 0x0 0x4000>;
1142 #phy-cells = <0>;
1143 nvidia,hssync-start-delay = <0>;
1148 nvidia,xcvr-lsfslew = <0>;
1158 reg = <0x0 0x7d008000 0x0 0x4000>;
1170 reg = <0x0 0x7d008000 0x0 0x4000>,
1171 <0x0 0x7d000000 0x0 0x4000>;
1179 #phy-cells = <0>;
1180 nvidia,hssync-start-delay = <0>;
1185 nvidia,xcvr-lsfslew = <0>;
1195 #size-cells = <0>;
1197 cpu@0 {
1200 reg = <0>;
1237 interrupt-affinity = <&{/cpus/cpu@0}>,
1254 hysteresis = <0>;
1282 hysteresis = <0>;
1310 hysteresis = <0>;
1338 hysteresis = <0>;