Lines Matching full:ccu
45 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
46 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
64 <&ccu CLK_TCON0>;
77 clocks = <&ccu CLK_CPU>;
126 clocks = <&ccu CLK_BUS_DE>,
127 <&ccu CLK_DE>;
130 resets = <&ccu RST_BUS_DE>;
180 clocks = <&ccu CLK_BUS_DMA>;
181 resets = <&ccu RST_BUS_DMA>;
189 clocks = <&ccu CLK_BUS_TCON0>,
190 <&ccu CLK_TCON0>;
195 resets = <&ccu RST_BUS_TCON0>;
223 clocks = <&ccu CLK_BUS_MMC0>,
224 <&ccu CLK_MMC0>,
225 <&ccu CLK_MMC0_OUTPUT>,
226 <&ccu CLK_MMC0_SAMPLE>;
231 resets = <&ccu RST_BUS_MMC0>;
244 clocks = <&ccu CLK_BUS_MMC1>,
245 <&ccu CLK_MMC1>,
246 <&ccu CLK_MMC1_OUTPUT>,
247 <&ccu CLK_MMC1_SAMPLE>;
252 resets = <&ccu RST_BUS_MMC1>;
265 clocks = <&ccu CLK_BUS_MMC2>,
266 <&ccu CLK_MMC2>,
267 <&ccu CLK_MMC2_OUTPUT>,
268 <&ccu CLK_MMC2_SAMPLE>;
273 resets = <&ccu RST_BUS_MMC2>;
286 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
290 resets = <&ccu RST_BUS_CE>;
297 clocks = <&ccu CLK_BUS_OTG>;
298 resets = <&ccu RST_BUS_OTG>;
313 clocks = <&ccu CLK_USB_PHY0>;
315 resets = <&ccu RST_USB_PHY0>;
321 ccu: clock@1c20000 { label
322 compatible = "allwinner,sun8i-v3s-ccu";
345 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
458 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
460 resets = <&ccu RST_BUS_CODEC>;
478 clocks = <&ccu CLK_BUS_UART0>;
481 resets = <&ccu RST_BUS_UART0>;
491 clocks = <&ccu CLK_BUS_UART1>;
494 resets = <&ccu RST_BUS_UART1>;
504 clocks = <&ccu CLK_BUS_UART2>;
507 resets = <&ccu RST_BUS_UART2>;
517 clocks = <&ccu CLK_BUS_I2C0>;
518 resets = <&ccu RST_BUS_I2C0>;
530 clocks = <&ccu CLK_BUS_I2C1>;
531 resets = <&ccu RST_BUS_I2C1>;
543 resets = <&ccu RST_BUS_EMAC>;
545 clocks = <&ccu CLK_BUS_EMAC>;
573 clocks = <&ccu CLK_BUS_EPHY>;
574 resets = <&ccu RST_BUS_EPHY>;
584 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
590 resets = <&ccu RST_BUS_SPI0>;
600 clocks = <&ccu CLK_BUS_CSI>,
601 <&ccu CLK_CSI1_SCLK>,
602 <&ccu CLK_DRAM_CSI>;
604 resets = <&ccu RST_BUS_CSI>;