Lines Matching +full:0 +full:x01c00000
71 #size-cells = <0>;
73 cpu@0 {
76 reg = <0>;
101 #clock-cells = <0>;
109 #clock-cells = <0>;
125 reg = <0x01000000 0x10000>;
137 reg = <0x01100000 0x100000>;
138 clocks = <&display_clocks 0>,
142 resets = <&display_clocks 0>;
146 #size-cells = <0>;
161 reg = <0x01c00000 0xd0>;
172 reg = <0x01c000d0 0x0c>;
178 reg = <0x01c02000 0x1000>;
187 reg = <0x01c0c000 0x1000>;
194 #clock-cells = <0>;
201 #size-cells = <0>;
203 tcon0_in: port@0 {
204 reg = <0>;
213 #size-cells = <0>;
222 reg = <0x01c0f000 0x1000>;
235 pinctrl-0 = <&mmc0_pins>;
238 #size-cells = <0>;
243 reg = <0x01c10000 0x1000>;
256 pinctrl-0 = <&mmc1_pins>;
259 #size-cells = <0>;
264 reg = <0x01c11000 0x1000>;
278 #size-cells = <0>;
284 reg = <0x01c15000 0x1000>;
296 reg = <0x01c19000 0x0400>;
301 phys = <&usbphy 0>;
303 extcon = <&usbphy 0>;
309 reg = <0x01c19400 0x2c>,
310 <0x01c1a800 0x4>;
323 reg = <0x01c20000 0x400>;
324 clocks = <&osc24M>, <&rtc 0>;
333 reg = <0x01c20400 0x54>;
342 reg = <0x01c20800 0x400>;
345 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
423 reg = <0x01c20c00 0xa0>;
432 reg = <0x01c20ca0 0x20>;
440 reg = <0x01c21400 0xc>;
448 reg = <0x01c22800 0x400>;
454 #sound-dai-cells = <0>;
456 reg = <0x01c22c00 0x400>;
469 reg = <0x01c23000 0x4>;
474 reg = <0x01c28000 0x400>;
475 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
487 reg = <0x01c28400 0x400>;
500 reg = <0x01c28800 0x400>;
508 pinctrl-0 = <&uart2_pins>;
515 reg = <0x01c2ac00 0x400>;
520 pinctrl-0 = <&i2c0_pins>;
523 #size-cells = <0>;
528 reg = <0x01c2b000 0x400>;
534 #size-cells = <0>;
540 reg = <0x01c30000 0x10000>;
553 #size-cells = <0>;
560 #size-cells = <0>;
568 #size-cells = <0>;
582 reg = <0x01c68000 0x1000>;
589 pinctrl-0 = <&spi0_pins>;
593 #size-cells = <0>;
598 reg = <0x01cb4000 0x3000>;
610 reg = <0x01c81000 0x1000>,
611 <0x01c82000 0x2000>,
612 <0x01c84000 0x2000>,
613 <0x01c86000 0x2000>;