Lines Matching full:ccu
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
140 clocks = <&ccu CLK_BUS_DE>,
141 <&ccu CLK_DE>;
144 resets = <&ccu RST_BUS_DE>;
197 clocks = <&ccu CLK_BUS_DEINTERLACE>,
198 <&ccu CLK_DEINTERLACE>,
204 <&ccu CLK_DRAM_CSI1>;
206 resets = <&ccu RST_BUS_DEINTERLACE>;
248 clocks = <&ccu CLK_BUS_DMA>;
251 resets = <&ccu RST_BUS_DMA>;
260 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
262 resets = <&ccu RST_BUS_SPI0>;
273 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
275 resets = <&ccu RST_BUS_SPI1>;
286 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
287 <&ccu CLK_DRAM_CSI0>;
289 resets = <&ccu RST_BUS_CSI0>;
298 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
299 <&ccu CLK_DRAM_VE>;
301 resets = <&ccu RST_BUS_VE>;
310 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
312 resets = <&ccu RST_BUS_MMC0>;
326 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
328 resets = <&ccu RST_BUS_MMC1>;
340 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
342 resets = <&ccu RST_BUS_MMC2>;
356 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
358 resets = <&ccu RST_BUS_MMC3>;
378 clocks = <&ccu CLK_USB_PHY0>,
379 <&ccu CLK_USB_PHY1>,
380 <&ccu CLK_USB_PHY2>;
384 resets = <&ccu RST_USB_PHY0>,
385 <&ccu RST_USB_PHY1>,
386 <&ccu RST_USB_PHY2>;
398 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
400 resets = <&ccu RST_BUS_CE>;
408 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
410 resets = <&ccu RST_BUS_SPI2>;
420 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
421 resets = <&ccu RST_BUS_SATA>;
430 clocks = <&ccu CLK_BUS_EHCI1>;
431 resets = <&ccu RST_BUS_EHCI1>;
441 clocks = <&ccu CLK_BUS_OHCI1>,
442 <&ccu CLK_USB_OHCI1>;
443 resets = <&ccu RST_BUS_OHCI1>;
453 clocks = <&ccu CLK_BUS_EHCI2>;
454 resets = <&ccu RST_BUS_EHCI2>;
464 clocks = <&ccu CLK_BUS_OHCI2>,
465 <&ccu CLK_USB_OHCI2>;
466 resets = <&ccu RST_BUS_OHCI2>;
477 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
479 resets = <&ccu RST_BUS_SPI3>;
485 ccu: clock@1c20000 { label
486 compatible = "allwinner,sun8i-r40-ccu";
507 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
719 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
722 resets = <&ccu RST_BUS_IR0>;
732 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
735 resets = <&ccu RST_BUS_IR1>;
742 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
745 resets = <&ccu RST_BUS_THS>;
756 clocks = <&ccu CLK_BUS_UART0>;
757 resets = <&ccu RST_BUS_UART0>;
767 clocks = <&ccu CLK_BUS_UART1>;
768 resets = <&ccu RST_BUS_UART1>;
778 clocks = <&ccu CLK_BUS_UART2>;
779 resets = <&ccu RST_BUS_UART2>;
789 clocks = <&ccu CLK_BUS_UART3>;
790 resets = <&ccu RST_BUS_UART3>;
800 clocks = <&ccu CLK_BUS_UART4>;
801 resets = <&ccu RST_BUS_UART4>;
811 clocks = <&ccu CLK_BUS_UART5>;
812 resets = <&ccu RST_BUS_UART5>;
822 clocks = <&ccu CLK_BUS_UART6>;
823 resets = <&ccu RST_BUS_UART6>;
833 clocks = <&ccu CLK_BUS_UART7>;
834 resets = <&ccu RST_BUS_UART7>;
842 clocks = <&ccu CLK_BUS_I2C0>;
843 resets = <&ccu RST_BUS_I2C0>;
855 clocks = <&ccu CLK_BUS_I2C1>;
856 resets = <&ccu RST_BUS_I2C1>;
868 clocks = <&ccu CLK_BUS_I2C2>;
869 resets = <&ccu RST_BUS_I2C2>;
881 clocks = <&ccu CLK_BUS_I2C3>;
882 resets = <&ccu RST_BUS_I2C3>;
894 clocks = <&ccu CLK_BUS_I2C4>;
895 resets = <&ccu RST_BUS_I2C4>;
920 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
922 resets = <&ccu RST_BUS_GPU>;
927 syscon = <&ccu>;
931 resets = <&ccu RST_BUS_GMAC>;
933 clocks = <&ccu CLK_BUS_GMAC>;
947 clocks = <&ccu 155>;
957 clocks = <&ccu CLK_BUS_TCON_TOP>,
958 <&ccu CLK_TCON_TV0>,
959 <&ccu CLK_TVE0>,
960 <&ccu CLK_TCON_TV1>,
961 <&ccu CLK_TVE1>,
962 <&ccu CLK_DSI_DPHY>;
972 resets = <&ccu RST_BUS_TCON_TOP>;
1076 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
1078 resets = <&ccu RST_BUS_TCON_TV0>;
1119 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
1121 resets = <&ccu RST_BUS_TCON_TV1>;
1175 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
1176 <&ccu CLK_HDMI>;
1178 resets = <&ccu RST_BUS_HDMI1>;
1205 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1206 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1208 resets = <&ccu RST_BUS_HDMI0>;