Lines Matching +full:0 +full:x01c06000
63 #clock-cells = <0>;
71 #clock-cells = <0>;
81 #size-cells = <0>;
83 cpu0: cpu@0 {
86 reg = <0>;
117 polling-delay-passive = <0>;
118 polling-delay = <0>;
119 thermal-sensors = <&ths 0>;
124 polling-delay-passive = <0>;
125 polling-delay = <0>;
139 reg = <0x01000000 0x10000>;
150 compatible = "allwinner,sun8i-r40-de2-mixer-0";
151 reg = <0x01100000 0x100000>;
160 #size-cells = <0>;
173 reg = <0x01200000 0x100000>;
182 #size-cells = <0>;
196 reg = <0x01400000 0x20000>;
215 reg = <0x01c00000 0x30>;
222 reg = <0x01d00000 0xd0000>;
225 ranges = <0 0x01d00000 0xd0000>;
227 ve_sram: sram-section@0 {
230 reg = <0x000000 0x80000>;
239 reg = <0x01c00030 0x0c>;
240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
246 reg = <0x01c02000 0x1000>;
258 reg = <0x01c05000 0x1000>;
265 #size-cells = <0>;
271 reg = <0x01c06000 0x1000>;
278 #size-cells = <0>;
284 reg = <0x01c09000 0x1000>;
297 reg = <0x01c0e000 0x1000>;
309 reg = <0x01c0f000 0x1000>;
314 pinctrl-0 = <&mmc0_pins>;
319 #size-cells = <0>;
325 reg = <0x01c10000 0x1000>;
333 #size-cells = <0>;
339 reg = <0x01c11000 0x1000>;
344 pinctrl-0 = <&mmc2_pins>;
349 #size-cells = <0>;
355 reg = <0x01c12000 0x1000>;
360 pinctrl-0 = <&mmc3_pins>;
365 #size-cells = <0>;
370 reg = <0x01c13400 0x14>,
371 <0x01c14800 0x4>,
372 <0x01c19800 0x4>,
373 <0x01c1c800 0x4>;
396 reg = <0x01c15000 0x1000>;
406 reg = <0x01c17000 0x1000>;
413 #size-cells = <0>;
418 reg = <0x01c18000 0x1000>;
428 reg = <0x01c19000 0x100>;
439 reg = <0x01c19400 0x100>;
451 reg = <0x01c1c000 0x100>;
462 reg = <0x01c1c400 0x100>;
475 reg = <0x01c1f000 0x1000>;
482 #size-cells = <0>;
487 reg = <0x01c20000 0x400>;
488 clocks = <&osc24M>, <&rtc 0>;
496 reg = <0x01c20400 0x400>;
505 reg = <0x01c20800 0x400>;
507 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
696 reg = <0x01c20c00 0x90>;
708 reg = <0x01c20c90 0x10>;
716 reg = <0x01c21800 0x400>;
717 pinctrl-0 = <&ir0_pins>;
729 reg = <0x01c21c00 0x400>;
730 pinctrl-0 = <&ir1_pins>;
741 reg = <0x01c24c00 0x100>;
752 reg = <0x01c28000 0x400>;
763 reg = <0x01c28400 0x400>;
774 reg = <0x01c28800 0x400>;
785 reg = <0x01c28c00 0x400>;
796 reg = <0x01c29000 0x400>;
807 reg = <0x01c29400 0x400>;
818 reg = <0x01c29800 0x400>;
829 reg = <0x01c29c00 0x400>;
840 reg = <0x01c2ac00 0x400>;
844 pinctrl-0 = <&i2c0_pins>;
848 #size-cells = <0>;
853 reg = <0x01c2b000 0x400>;
857 pinctrl-0 = <&i2c1_pins>;
861 #size-cells = <0>;
866 reg = <0x01c2b400 0x400>;
870 pinctrl-0 = <&i2c2_pins>;
874 #size-cells = <0>;
879 reg = <0x01c2b800 0x400>;
883 pinctrl-0 = <&i2c3_pins>;
887 #size-cells = <0>;
892 reg = <0x01c2c000 0x400>;
896 pinctrl-0 = <&i2c4_pins>;
900 #size-cells = <0>;
905 reg = <0x01c40000 0x10000>;
928 reg = <0x01c50000 0x10000>;
940 #size-cells = <0>;
946 reg = <0x01c62000 0x1000>;
950 dma-ranges = <0x00000000 0x40000000 0x80000000>;
956 reg = <0x01c70000 0x1000>;
977 #size-cells = <0>;
979 tcon_top_mixer0_in: port@0 {
980 reg = <0>;
989 #size-cells = <0>;
992 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
993 reg = <0>;
1013 #size-cells = <0>;
1024 #size-cells = <0>;
1027 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1028 reg = <0>;
1048 #size-cells = <0>;
1051 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
1052 reg = <0>;
1074 reg = <0x01c73000 0x1000>;
1084 #size-cells = <0>;
1086 tcon_tv0_in: port@0 {
1088 #size-cells = <0>;
1089 reg = <0>;
1091 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1092 reg = <0>;
1104 #size-cells = <0>;
1117 reg = <0x01c74000 0x1000>;
1127 #size-cells = <0>;
1129 tcon_tv1_in: port@0 {
1131 #size-cells = <0>;
1132 reg = <0>;
1134 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1135 reg = <0>;
1147 #size-cells = <0>;
1160 reg = <0x01c81000 0x1000>,
1161 <0x01c82000 0x2000>,
1162 <0x01c84000 0x2000>,
1163 <0x01c86000 0x2000>;
1172 reg = <0x01ee0000 0x10000>;
1186 #size-cells = <0>;
1188 hdmi_in: port@0 {
1189 reg = <0>;
1204 reg = <0x01ef0000 0x10000>;
1207 clock-names = "bus", "mod", "pll-0", "pll-1";
1210 #phy-cells = <0>;