Lines Matching +full:sun8i +full:- +full:a23 +full:- +full:a33 +full:- +full:ccu
2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
51 interrupt-parent = <&gic>;
52 #address-cells = <1>;
53 #size-cells = <1>;
56 #address-cells = <1>;
57 #size-cells = <1>;
60 simplefb_lcd: framebuffer-lcd0 {
61 compatible = "allwinner,simple-framebuffer",
62 "simple-framebuffer";
63 allwinner,pipeline = "de_be0-lcd0";
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
71 de: display-engine {
78 compatible = "arm,armv7-timer";
83 clock-frequency = <24000000>;
84 arm,cpu-registers-not-fw-configured;
88 enable-method = "allwinner,sun8i-a23";
89 #address-cells = <1>;
90 #size-cells = <0>;
93 compatible = "arm,cortex-a7";
99 compatible = "arm,cortex-a7";
106 #address-cells = <1>;
107 #size-cells = <1>;
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <24000000>;
114 clock-accuracy = <50000>;
115 clock-output-names = "osc24M";
119 #clock-cells = <0>;
120 compatible = "fixed-clock";
121 clock-frequency = <32768>;
122 clock-accuracy = <50000>;
123 clock-output-names = "ext-osc32k";
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
133 system-control@1c00000 {
134 compatible = "allwinner,sun8i-a23-system-control";
136 #address-cells = <1>;
137 #size-cells = <1>;
141 compatible = "mmio-sram";
143 #address-cells = <1>;
144 #size-cells = <1>;
147 ve_sram: sram-section@0 {
148 compatible = "allwinner,sun8i-a23-sram-c1",
149 "allwinner,sun4i-a10-sram-c1";
155 dma: dma-controller@1c02000 {
156 compatible = "allwinner,sun8i-a23-dma";
159 clocks = <&ccu CLK_BUS_DMA>;
160 resets = <&ccu RST_BUS_DMA>;
161 #dma-cells = <1>;
164 nfc: nand-controller@1c03000 {
165 compatible = "allwinner,sun8i-a23-nand-controller";
168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
169 clock-names = "ahb", "mod";
170 resets = <&ccu RST_BUS_NAND>;
171 reset-names = "ahb";
173 dma-names = "rxtx";
174 pinctrl-names = "default";
175 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
177 #address-cells = <1>;
178 #size-cells = <0>;
181 tcon0: lcd-controller@1c0c000 {
186 clocks = <&ccu CLK_BUS_LCD>,
187 <&ccu CLK_LCD_CH0>,
188 <&ccu 13>;
189 clock-names = "ahb",
190 "tcon-ch0",
191 "lvds-alt";
192 clock-output-names = "tcon-pixel-clock";
193 #clock-cells = <0>;
194 resets = <&ccu RST_BUS_LCD>,
195 <&ccu RST_BUS_LVDS>;
196 reset-names = "lcd",
201 #address-cells = <1>;
202 #size-cells = <0>;
208 remote-endpoint = <&drc0_out_tcon0>;
219 compatible = "allwinner,sun7i-a20-mmc";
221 clocks = <&ccu CLK_BUS_MMC0>,
222 <&ccu CLK_MMC0>,
223 <&ccu CLK_MMC0_OUTPUT>,
224 <&ccu CLK_MMC0_SAMPLE>;
225 clock-names = "ahb",
229 resets = <&ccu RST_BUS_MMC0>;
230 reset-names = "ahb";
232 pinctrl-names = "default";
233 pinctrl-0 = <&mmc0_pins>;
235 #address-cells = <1>;
236 #size-cells = <0>;
240 compatible = "allwinner,sun7i-a20-mmc";
242 clocks = <&ccu CLK_BUS_MMC1>,
243 <&ccu CLK_MMC1>,
244 <&ccu CLK_MMC1_OUTPUT>,
245 <&ccu CLK_MMC1_SAMPLE>;
246 clock-names = "ahb",
250 resets = <&ccu RST_BUS_MMC1>;
251 reset-names = "ahb";
254 #address-cells = <1>;
255 #size-cells = <0>;
259 compatible = "allwinner,sun7i-a20-mmc";
261 clocks = <&ccu CLK_BUS_MMC2>,
262 <&ccu CLK_MMC2>,
263 <&ccu CLK_MMC2_OUTPUT>,
264 <&ccu CLK_MMC2_SAMPLE>;
265 clock-names = "ahb",
269 resets = <&ccu RST_BUS_MMC2>;
270 reset-names = "ahb";
273 #address-cells = <1>;
274 #size-cells = <0>;
280 clocks = <&ccu CLK_BUS_OTG>;
281 resets = <&ccu RST_BUS_OTG>;
283 interrupt-names = "mc";
285 phy-names = "usb";
296 clocks = <&ccu CLK_USB_PHY0>,
297 <&ccu CLK_USB_PHY1>;
298 clock-names = "usb0_phy",
300 resets = <&ccu RST_USB_PHY0>,
301 <&ccu RST_USB_PHY1>;
302 reset-names = "usb0_reset",
305 #phy-cells = <1>;
309 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
312 clocks = <&ccu CLK_BUS_EHCI>;
313 resets = <&ccu RST_BUS_EHCI>;
315 phy-names = "usb";
320 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
323 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
324 resets = <&ccu RST_BUS_OHCI>;
326 phy-names = "usb";
330 ccu: clock@1c20000 { label
333 clock-names = "hosc", "losc";
334 #clock-cells = <1>;
335 #reset-cells = <1>;
341 interrupt-parent = <&r_intc>;
343 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
344 clock-names = "apb", "hosc", "losc";
345 gpio-controller;
346 interrupt-controller;
347 #interrupt-cells = <3>;
348 #gpio-cells = <3>;
350 i2c0_pins: i2c0-pins {
355 i2c1_pins: i2c1-pins {
360 i2c2_pins: i2c2-pins {
365 lcd_rgb666_pins: lcd-rgb666-pins {
373 mmc0_pins: mmc0-pins {
377 drive-strength = <30>;
378 bias-pull-up;
381 mmc1_pg_pins: mmc1-pg-pins {
385 drive-strength = <30>;
386 bias-pull-up;
389 mmc2_8bit_pins: mmc2-8bit-pins {
395 drive-strength = <30>;
396 bias-pull-up;
399 nand_pins: nand-pins {
406 nand_cs0_pin: nand-cs0-pin {
409 bias-pull-up;
412 nand_cs1_pin: nand-cs1-pin {
415 bias-pull-up;
418 nand_rb0_pin: nand-rb0-pin {
421 bias-pull-up;
424 nand_rb1_pin: nand-rb1-pin {
427 bias-pull-up;
430 pwm0_pin: pwm0-pin {
435 uart0_pf_pins: uart0-pf-pins {
440 uart1_pg_pins: uart1-pg-pins {
445 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
452 compatible = "allwinner,sun8i-a23-timer";
460 compatible = "allwinner,sun6i-a31-wdt";
467 compatible = "allwinner,sun7i-a20-pwm";
470 #pwm-cells = <3>;
475 compatible = "allwinner,sun4i-a10-lradc-keys";
477 interrupt-parent = <&r_intc>;
483 compatible = "snps,dw-apb-uart";
486 reg-shift = <2>;
487 reg-io-width = <4>;
488 clocks = <&ccu CLK_BUS_UART0>;
489 resets = <&ccu RST_BUS_UART0>;
491 dma-names = "rx", "tx";
496 compatible = "snps,dw-apb-uart";
499 reg-shift = <2>;
500 reg-io-width = <4>;
501 clocks = <&ccu CLK_BUS_UART1>;
502 resets = <&ccu RST_BUS_UART1>;
504 dma-names = "rx", "tx";
509 compatible = "snps,dw-apb-uart";
512 reg-shift = <2>;
513 reg-io-width = <4>;
514 clocks = <&ccu CLK_BUS_UART2>;
515 resets = <&ccu RST_BUS_UART2>;
517 dma-names = "rx", "tx";
522 compatible = "snps,dw-apb-uart";
525 reg-shift = <2>;
526 reg-io-width = <4>;
527 clocks = <&ccu CLK_BUS_UART3>;
528 resets = <&ccu RST_BUS_UART3>;
530 dma-names = "rx", "tx";
535 compatible = "snps,dw-apb-uart";
538 reg-shift = <2>;
539 reg-io-width = <4>;
540 clocks = <&ccu CLK_BUS_UART4>;
541 resets = <&ccu RST_BUS_UART4>;
543 dma-names = "rx", "tx";
548 compatible = "allwinner,sun6i-a31-i2c";
551 clocks = <&ccu CLK_BUS_I2C0>;
552 resets = <&ccu RST_BUS_I2C0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c0_pins>;
556 #address-cells = <1>;
557 #size-cells = <0>;
561 compatible = "allwinner,sun6i-a31-i2c";
564 clocks = <&ccu CLK_BUS_I2C1>;
565 resets = <&ccu RST_BUS_I2C1>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c1_pins>;
569 #address-cells = <1>;
570 #size-cells = <0>;
574 compatible = "allwinner,sun6i-a31-i2c";
577 clocks = <&ccu CLK_BUS_I2C2>;
578 resets = <&ccu RST_BUS_I2C2>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c2_pins>;
582 #address-cells = <1>;
583 #size-cells = <0>;
587 compatible = "allwinner,sun8i-a23-mali",
588 "allwinner,sun7i-a20-mali", "arm,mali-400";
597 interrupt-names = "gp",
604 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
605 clock-names = "bus", "core";
606 resets = <&ccu RST_BUS_GPU>;
607 #cooling-cells = <2>;
609 assigned-clocks = <&ccu CLK_GPU>;
610 assigned-clock-rates = <384000000>;
613 gic: interrupt-controller@1c81000 {
614 compatible = "arm,gic-400";
619 interrupt-controller;
620 #interrupt-cells = <3>;
624 fe0: display-frontend@1e00000 {
628 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
629 <&ccu CLK_DRAM_DE_FE>;
630 clock-names = "ahb", "mod",
632 resets = <&ccu RST_BUS_DE_FE>;
635 #address-cells = <1>;
636 #size-cells = <0>;
642 remote-endpoint = <&be0_in_fe0>;
648 be0: display-backend@1e60000 {
652 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
653 <&ccu CLK_DRAM_DE_BE>;
654 clock-names = "ahb", "mod",
656 resets = <&ccu RST_BUS_DE_BE>;
659 #address-cells = <1>;
660 #size-cells = <0>;
666 remote-endpoint = <&fe0_out_be0>;
674 remote-endpoint = <&drc0_in_be0>;
684 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
685 <&ccu CLK_DRAM_DRC>;
686 clock-names = "ahb", "mod", "ram";
687 resets = <&ccu RST_BUS_DRC>;
690 #address-cells = <1>;
691 #size-cells = <0>;
697 remote-endpoint = <&be0_out_drc0>;
705 remote-endpoint = <&tcon0_in_drc0>;
712 compatible = "allwinner,sun8i-a23-rtc";
714 interrupt-parent = <&r_intc>;
717 clock-output-names = "osc32k", "osc32k-out";
719 #clock-cells = <1>;
722 r_intc: interrupt-controller@1f00c00 {
723 compatible = "allwinner,sun6i-a31-r-intc";
724 interrupt-controller;
725 #interrupt-cells = <3>;
731 compatible = "allwinner,sun8i-a23-prcm";
735 compatible = "fixed-factor-clock";
736 #clock-cells = <0>;
737 clock-div = <1>;
738 clock-mult = <1>;
740 clock-output-names = "ar100";
744 compatible = "fixed-factor-clock";
745 #clock-cells = <0>;
746 clock-div = <1>;
747 clock-mult = <1>;
749 clock-output-names = "ahb0";
753 compatible = "allwinner,sun8i-a23-apb0-clk";
754 #clock-cells = <0>;
756 clock-output-names = "apb0";
760 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
761 #clock-cells = <1>;
763 clock-output-names = "apb0_pio", "apb0_timer",
769 compatible = "allwinner,sun6i-a31-clock-reset";
770 #reset-cells = <1>;
773 codec_analog: codec-analog {
774 compatible = "allwinner,sun8i-a23-codec-analog";
779 compatible = "allwinner,sun8i-a23-cpuconfig";
784 compatible = "snps,dw-apb-uart";
787 reg-shift = <2>;
788 reg-io-width = <4>;
795 compatible = "allwinner,sun8i-a23-i2c",
796 "allwinner,sun6i-a31-i2c";
799 pinctrl-names = "default";
800 pinctrl-0 = <&r_i2c_pins>;
804 #address-cells = <1>;
805 #size-cells = <0>;
809 compatible = "allwinner,sun8i-a23-r-pinctrl";
811 interrupt-parent = <&r_intc>;
814 clock-names = "apb", "hosc", "losc";
816 gpio-controller;
817 interrupt-controller;
818 #interrupt-cells = <3>;
819 #gpio-cells = <3>;
821 r_i2c_pins: r-i2c-pins {
824 bias-pull-up;
827 r_rsb_pins: r-rsb-pins {
830 drive-strength = <20>;
831 bias-pull-up;
834 r_uart_pins_a: r-uart-pins {
841 compatible = "allwinner,sun8i-a23-rsb";
845 clock-frequency = <3000000>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&r_rsb_pins>;
850 #address-cells = <1>;
851 #size-cells = <0>;