Lines Matching +full:0 +full:x01e60000
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
216 #clock-cells = <0>;
224 #clock-cells = <0>;
241 #clock-cells = <0>;
248 #clock-cells = <0>;
255 #clock-cells = <0>;
257 reg = <0x01c200d0 0x4>;
277 reg = <0x01c02000 0x1000>;
286 reg = <0x01c0c000 0x1000>;
302 #clock-cells = <0>;
306 #size-cells = <0>;
308 tcon0_in: port@0 {
310 #size-cells = <0>;
311 reg = <0>;
313 tcon0_in_drc0: endpoint@0 {
314 reg = <0>;
326 #size-cells = <0>;
340 reg = <0x01c0d000 0x1000>;
355 #clock-cells = <0>;
359 #size-cells = <0>;
361 tcon1_in: port@0 {
363 #size-cells = <0>;
364 reg = <0>;
366 tcon1_in_drc0: endpoint@0 {
367 reg = <0>;
379 #size-cells = <0>;
393 reg = <0x01c0f000 0x1000>;
406 pinctrl-0 = <&mmc0_pins>;
409 #size-cells = <0>;
414 reg = <0x01c10000 0x1000>;
427 pinctrl-0 = <&mmc1_pins>;
430 #size-cells = <0>;
435 reg = <0x01c11000 0x1000>;
449 #size-cells = <0>;
454 reg = <0x01c12000 0x1000>;
468 #size-cells = <0>;
473 reg = <0x01c16000 0x1000>;
479 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
487 #size-cells = <0>;
489 hdmi_in: port@0 {
491 #size-cells = <0>;
492 reg = <0>;
494 hdmi_in_tcon0: endpoint@0 {
495 reg = <0>;
513 reg = <0x01c19000 0x0400>;
518 phys = <&usbphy 0>;
520 extcon = <&usbphy 0>;
527 reg = <0x01c19400 0x10>,
528 <0x01c1a800 0x4>,
529 <0x01c1b800 0x4>;
551 reg = <0x01c1a000 0x100>;
562 reg = <0x01c1a400 0x100>;
573 reg = <0x01c1b000 0x100>;
584 reg = <0x01c1b400 0x100>;
595 reg = <0x01c1c400 0x100>;
604 reg = <0x01c20000 0x400>;
605 clocks = <&osc24M>, <&rtc 0>;
613 reg = <0x01c20800 0x400>;
619 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
747 reg = <0x01c20c00 0xa0>;
759 reg = <0x01c20ca0 0x20>;
765 #sound-dai-cells = <0>;
767 reg = <0x01c21000 0x400>;
778 #sound-dai-cells = <0>;
780 reg = <0x01c22000 0x400>;
791 #sound-dai-cells = <0>;
793 reg = <0x01c22400 0x400>;
805 reg = <0x01c22800 0x100>;
813 reg = <0x01c25000 0x100>;
815 #thermal-sensor-cells = <0>;
820 reg = <0x01c28000 0x400>;
821 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
833 reg = <0x01c28400 0x400>;
846 reg = <0x01c28800 0x400>;
859 reg = <0x01c28c00 0x400>;
872 reg = <0x01c29000 0x400>;
885 reg = <0x01c29400 0x400>;
898 reg = <0x01c2ac00 0x400>;
903 pinctrl-0 = <&i2c0_pins>;
906 #size-cells = <0>;
911 reg = <0x01c2b000 0x400>;
916 pinctrl-0 = <&i2c1_pins>;
919 #size-cells = <0>;
924 reg = <0x01c2b400 0x400>;
929 pinctrl-0 = <&i2c2_pins>;
932 #size-cells = <0>;
937 reg = <0x01c2b800 0x400>;
943 #size-cells = <0>;
948 reg = <0x01c30000 0x1054>;
963 #size-cells = <0>;
970 reg = <0x01c15000 0x1000>;
979 #sound-dai-cells = <0>;
981 reg = <0x01c22c00 0x400>;
994 reg = <0x01c60000 0x1000>;
1005 reg = <0x01c68000 0x1000>;
1014 #size-cells = <0>;
1019 reg = <0x01c69000 0x1000>;
1028 #size-cells = <0>;
1033 reg = <0x01c6a000 0x1000>;
1042 #size-cells = <0>;
1047 reg = <0x01c6b000 0x1000>;
1056 #size-cells = <0>;
1061 reg = <0x01c81000 0x1000>,
1062 <0x01c82000 0x2000>,
1063 <0x01c84000 0x2000>,
1064 <0x01c86000 0x2000>;
1072 reg = <0x01e00000 0x20000>;
1082 #size-cells = <0>;
1086 #size-cells = <0>;
1089 fe0_out_be0: endpoint@0 {
1090 reg = <0>;
1104 reg = <0x01e20000 0x20000>;
1114 #size-cells = <0>;
1118 #size-cells = <0>;
1121 fe1_out_be0: endpoint@0 {
1122 reg = <0>;
1136 reg = <0x01e40000 0x10000>;
1146 #size-cells = <0>;
1148 be1_in: port@0 {
1150 #size-cells = <0>;
1151 reg = <0>;
1153 be1_in_fe0: endpoint@0 {
1154 reg = <0>;
1166 #size-cells = <0>;
1179 reg = <0x01e50000 0x10000>;
1189 #size-cells = <0>;
1191 drc1_in: port@0 {
1193 #size-cells = <0>;
1194 reg = <0>;
1204 #size-cells = <0>;
1207 drc1_out_tcon0: endpoint@0 {
1208 reg = <0>;
1222 reg = <0x01e60000 0x10000>;
1232 #size-cells = <0>;
1234 be0_in: port@0 {
1236 #size-cells = <0>;
1237 reg = <0>;
1239 be0_in_fe0: endpoint@0 {
1240 reg = <0>;
1262 reg = <0x01e70000 0x10000>;
1272 #size-cells = <0>;
1274 drc0_in: port@0 {
1275 reg = <0>;
1284 #size-cells = <0>;
1287 drc0_out_tcon0: endpoint@0 {
1288 reg = <0>;
1303 reg = <0x01f00000 0x54>;
1315 reg = <0x01f00c00 0x400>;
1321 reg = <0x01f01400 0x200>;
1325 #clock-cells = <0>;
1326 clocks = <&rtc 0>, <&osc24M>,
1334 #clock-cells = <0>;
1343 #clock-cells = <0>;
1359 #clock-cells = <0>;
1361 clocks = <&rtc 0>, <&osc24M>;
1373 reg = <0x01f01c00 0x300>;
1382 reg = <0x01f02000 0x40>;
1388 reg = <0x01f02c00 0x400>;
1392 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
1394 resets = <&apb0_rst 0>;
1413 reg = <0x01f03400 0x400>;
1419 pinctrl-0 = <&s_p2wi_pins>;
1422 #size-cells = <0>;