Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 adc1_in6_pins_a: adc1-in6-0 {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
15 adc12_ain_pins_a: adc12-ain-0 {
18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
24 adc12_ain_pins_b: adc12-ain-1 {
26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
38 cec_pins_a: cec-0 {
40 pinmux = <STM32_PINMUX('A', 15, AF4)>;
41 bias-disable;
42 drive-open-drain;
43 slew-rate = <0>;
47 cec_sleep_pins_a: cec-sleep-0 {
49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
53 cec_pins_b: cec-1 {
56 bias-disable;
57 drive-open-drain;
58 slew-rate = <0>;
62 cec_sleep_pins_b: cec-sleep-1 {
68 dac_ch1_pins_a: dac-ch1-0 {
70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
74 dac_ch2_pins_a: dac-ch2-0 {
76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
80 dcmi_pins_a: dcmi-0 {
84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
97 bias-disable;
101 dcmi_sleep_pins_a: dcmi-sleep-0 {
105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
121 dcmi_pins_b: dcmi-1 {
123 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
125 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
133 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
134 bias-disable;
138 dcmi_sleep_pins_b: dcmi-sleep-1 {
140 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
142 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
150 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
154 ethernet0_rgmii_pins_a: rgmii-0 {
164 bias-disable;
165 drive-push-pull;
166 slew-rate = <2>;
169 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
170 bias-disable;
171 drive-push-pull;
172 slew-rate = <0>;
177 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
179 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
180 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
181 bias-disable;
185 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
194 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
198 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
200 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
201 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
205 ethernet0_rgmii_pins_b: rgmii-1 {
215 bias-disable;
216 drive-push-pull;
217 slew-rate = <2>;
220 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
221 bias-disable;
222 drive-push-pull;
223 slew-rate = <0>;
230 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
231 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
232 bias-disable;
236 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
246 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
251 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
252 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
256 ethernet0_rgmii_pins_c: rgmii-2 {
266 bias-disable;
267 drive-push-pull;
268 slew-rate = <2>;
271 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
272 bias-disable;
273 drive-push-pull;
274 slew-rate = <0>;
281 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
282 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
283 bias-disable;
287 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
296 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
302 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
303 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
307 ethernet0_rmii_pins_a: rmii-0 {
312 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
313 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
315 bias-disable;
316 drive-push-pull;
317 slew-rate = <2>;
322 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
323 bias-disable;
327 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
332 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
336 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
337 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
341 fmc_pins_a: fmc-0 {
349 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
353 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
355 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
356 bias-disable;
357 drive-push-pull;
358 slew-rate = <1>;
362 bias-pull-up;
366 fmc_sleep_pins_a: fmc-sleep-0 {
374 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
378 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
381 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
385 fmc_pins_b: fmc-1 {
392 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
396 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
404 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
406 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
408 bias-disable;
409 drive-push-pull;
410 slew-rate = <3>;
414 fmc_sleep_pins_b: fmc-sleep-1 {
421 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
425 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
433 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
435 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
440 i2c1_pins_a: i2c1-0 {
443 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
444 bias-disable;
445 drive-open-drain;
446 slew-rate = <0>;
450 i2c1_sleep_pins_a: i2c1-sleep-0 {
453 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
457 i2c1_pins_b: i2c1-1 {
459 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
460 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
461 bias-disable;
462 drive-open-drain;
463 slew-rate = <0>;
467 i2c1_sleep_pins_b: i2c1-sleep-1 {
469 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
470 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
474 i2c2_pins_a: i2c2-0 {
478 bias-disable;
479 drive-open-drain;
480 slew-rate = <0>;
484 i2c2_sleep_pins_a: i2c2-sleep-0 {
491 i2c2_pins_b1: i2c2-1 {
494 bias-disable;
495 drive-open-drain;
496 slew-rate = <0>;
500 i2c2_sleep_pins_b1: i2c2-sleep-1 {
506 i2c2_pins_c: i2c2-2 {
508 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
510 bias-disable;
511 drive-open-drain;
512 slew-rate = <0>;
516 i2c2_pins_sleep_c: i2c2-sleep-2 {
518 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
523 i2c5_pins_a: i2c5-0 {
525 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
526 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
527 bias-disable;
528 drive-open-drain;
529 slew-rate = <0>;
533 i2c5_sleep_pins_a: i2c5-sleep-0 {
535 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
536 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
541 i2c5_pins_b: i2c5-1 {
543 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
545 bias-disable;
546 drive-open-drain;
547 slew-rate = <0>;
551 i2c5_sleep_pins_b: i2c5-sleep-1 {
553 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
558 i2s2_pins_a: i2s2-0 {
561 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
562 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
563 slew-rate = <1>;
564 drive-push-pull;
565 bias-disable;
569 i2s2_sleep_pins_a: i2s2-sleep-0 {
572 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
573 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
577 ltdc_pins_a: ltdc-0 {
581 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
582 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
586 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
588 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
596 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
599 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
604 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
607 bias-disable;
608 drive-push-pull;
609 slew-rate = <1>;
613 ltdc_sleep_pins_a: ltdc-sleep-0 {
617 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
618 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
622 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
624 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
632 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
635 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
640 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
646 ltdc_pins_b: ltdc-1 {
653 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
662 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
665 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
676 bias-disable;
677 drive-push-pull;
678 slew-rate = <1>;
682 ltdc_sleep_pins_b: ltdc-sleep-1 {
689 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
698 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
701 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
715 ltdc_pins_c: ltdc-2 {
718 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
719 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */
729 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
736 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
738 bias-disable;
739 drive-push-pull;
740 slew-rate = <0>;
744 bias-disable;
745 drive-push-pull;
746 slew-rate = <1>;
750 ltdc_sleep_pins_c: ltdc-sleep-2 {
753 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
754 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */
764 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
771 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
777 ltdc_pins_d: ltdc-3 {
780 bias-disable;
781 drive-push-pull;
782 slew-rate = <3>;
786 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
791 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
792 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
797 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */
804 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
809 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
812 bias-disable;
813 drive-push-pull;
814 slew-rate = <2>;
818 ltdc_sleep_pins_d: ltdc-sleep-3 {
822 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
827 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
828 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
833 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */
840 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
845 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
851 m_can1_pins_a: m-can1-0 {
854 slew-rate = <1>;
855 drive-push-pull;
856 bias-disable;
859 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
860 bias-disable;
864 m_can1_sleep_pins_a: m_can1-sleep-0 {
867 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
871 m_can1_pins_b: m-can1-1 {
873 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
874 slew-rate = <1>;
875 drive-push-pull;
876 bias-disable;
879 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
880 bias-disable;
884 m_can1_sleep_pins_b: m_can1-sleep-1 {
886 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
887 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
891 m_can2_pins_a: m-can2-0 {
894 slew-rate = <1>;
895 drive-push-pull;
896 bias-disable;
900 bias-disable;
904 m_can2_sleep_pins_a: m_can2-sleep-0 {
911 pwm1_pins_a: pwm1-0 {
913 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
916 bias-pull-down;
917 drive-push-pull;
918 slew-rate = <0>;
922 pwm1_sleep_pins_a: pwm1-sleep-0 {
924 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
930 pwm2_pins_a: pwm2-0 {
932 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
933 bias-pull-down;
934 drive-push-pull;
935 slew-rate = <0>;
939 pwm2_sleep_pins_a: pwm2-sleep-0 {
941 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
945 pwm3_pins_a: pwm3-0 {
948 bias-pull-down;
949 drive-push-pull;
950 slew-rate = <0>;
954 pwm3_sleep_pins_a: pwm3-sleep-0 {
960 pwm3_pins_b: pwm3-1 {
963 bias-disable;
964 drive-push-pull;
965 slew-rate = <0>;
969 pwm3_sleep_pins_b: pwm3-sleep-1 {
975 pwm4_pins_a: pwm4-0 {
979 bias-pull-down;
980 drive-push-pull;
981 slew-rate = <0>;
985 pwm4_sleep_pins_a: pwm4-sleep-0 {
992 pwm4_pins_b: pwm4-1 {
995 bias-pull-down;
996 drive-push-pull;
997 slew-rate = <0>;
1001 pwm4_sleep_pins_b: pwm4-sleep-1 {
1007 pwm5_pins_a: pwm5-0 {
1010 bias-pull-down;
1011 drive-push-pull;
1012 slew-rate = <0>;
1016 pwm5_sleep_pins_a: pwm5-sleep-0 {
1022 pwm5_pins_b: pwm5-1 {
1026 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
1027 bias-disable;
1028 drive-push-pull;
1029 slew-rate = <0>;
1033 pwm5_sleep_pins_b: pwm5-sleep-1 {
1037 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
1041 pwm8_pins_a: pwm8-0 {
1044 bias-pull-down;
1045 drive-push-pull;
1046 slew-rate = <0>;
1050 pwm8_sleep_pins_a: pwm8-sleep-0 {
1056 pwm12_pins_a: pwm12-0 {
1059 bias-pull-down;
1060 drive-push-pull;
1061 slew-rate = <0>;
1065 pwm12_sleep_pins_a: pwm12-sleep-0 {
1071 qspi_clk_pins_a: qspi-clk-0 {
1073 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
1074 bias-disable;
1075 drive-push-pull;
1076 slew-rate = <3>;
1080 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
1082 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
1086 qspi_bk1_pins_a: qspi-bk1-0 {
1088 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
1089 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
1090 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
1091 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
1092 bias-disable;
1093 drive-push-pull;
1094 slew-rate = <1>;
1098 bias-pull-up;
1099 drive-push-pull;
1100 slew-rate = <1>;
1104 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
1106 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
1107 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
1108 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
1109 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
1114 qspi_bk2_pins_a: qspi-bk2-0 {
1120 bias-disable;
1121 drive-push-pull;
1122 slew-rate = <1>;
1125 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
1126 bias-pull-up;
1127 drive-push-pull;
1128 slew-rate = <1>;
1132 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
1138 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
1142 sai2a_pins_a: sai2a-0 {
1147 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
1148 slew-rate = <0>;
1149 drive-push-pull;
1150 bias-disable;
1154 sai2a_sleep_pins_a: sai2a-sleep-0 {
1159 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
1163 sai2a_pins_b: sai2a-1 {
1168 slew-rate = <0>;
1169 drive-push-pull;
1170 bias-disable;
1174 sai2a_sleep_pins_b: sai2a-sleep-1 {
1182 sai2a_pins_c: sai2a-4 {
1187 slew-rate = <0>;
1188 drive-push-pull;
1189 bias-disable;
1193 sai2a_sleep_pins_c: sai2a-5 {
1201 sai2b_pins_a: sai2b-0 {
1206 slew-rate = <0>;
1207 drive-push-pull;
1208 bias-disable;
1211 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1212 bias-disable;
1216 sai2b_sleep_pins_a: sai2b-sleep-0 {
1218 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
1225 sai2b_pins_b: sai2b-1 {
1227 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1228 bias-disable;
1232 sai2b_sleep_pins_b: sai2b-sleep-1 {
1234 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1238 sai2b_pins_c: sai2a-4 {
1240 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1241 bias-disable;
1245 sai2b_sleep_pins_c: sai2a-sleep-5 {
1247 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1251 sai4a_pins_a: sai4a-0 {
1254 slew-rate = <0>;
1255 drive-push-pull;
1256 bias-disable;
1260 sai4a_sleep_pins_a: sai4a-sleep-0 {
1266 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
1269 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1273 slew-rate = <1>;
1274 drive-push-pull;
1275 bias-disable;
1279 slew-rate = <2>;
1280 drive-push-pull;
1281 bias-disable;
1285 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
1288 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1291 slew-rate = <1>;
1292 drive-push-pull;
1293 bias-disable;
1297 slew-rate = <2>;
1298 drive-push-pull;
1299 bias-disable;
1303 slew-rate = <1>;
1304 drive-open-drain;
1305 bias-disable;
1309 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
1312 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1315 slew-rate = <1>;
1316 drive-push-pull;
1317 bias-disable;
1321 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
1324 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1332 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
1334 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1336 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1337 slew-rate = <1>;
1338 drive-push-pull;
1339 bias-pull-up;
1343 bias-pull-up;
1347 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
1349 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1351 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1352 slew-rate = <1>;
1353 drive-push-pull;
1354 bias-pull-up;
1358 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
1360 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
1362 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1367 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
1369 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1371 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1372 slew-rate = <1>;
1373 drive-push-pull;
1374 bias-pull-up;
1378 bias-pull-up;
1382 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
1384 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
1386 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1391 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
1398 slew-rate = <1>;
1399 drive-push-pull;
1400 bias-pull-up;
1404 slew-rate = <2>;
1405 drive-push-pull;
1406 bias-pull-up;
1410 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
1416 slew-rate = <1>;
1417 drive-push-pull;
1418 bias-pull-up;
1422 slew-rate = <2>;
1423 drive-push-pull;
1424 bias-pull-up;
1428 slew-rate = <1>;
1429 drive-open-drain;
1430 bias-pull-up;
1434 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
1445 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
1452 slew-rate = <1>;
1453 drive-push-pull;
1454 bias-disable;
1458 slew-rate = <2>;
1459 drive-push-pull;
1460 bias-disable;
1464 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
1470 slew-rate = <1>;
1471 drive-push-pull;
1472 bias-disable;
1476 slew-rate = <2>;
1477 drive-push-pull;
1478 bias-disable;
1482 slew-rate = <1>;
1483 drive-open-drain;
1484 bias-disable;
1488 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
1490 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1491 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1494 slew-rate = <1>;
1495 drive-push-pull;
1496 bias-pull-up;
1500 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
1502 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1503 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1509 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
1511 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1512 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1515 slew-rate = <1>;
1516 drive-push-pull;
1517 bias-disable;
1521 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
1523 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1524 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1530 sdmmc2_d47_pins_c: sdmmc2-d47-2 {
1532 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1533 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
1536 slew-rate = <1>;
1537 drive-push-pull;
1538 bias-pull-up;
1542 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
1544 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1545 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
1551 sdmmc2_d47_pins_d: sdmmc2-d47-3 {
1553 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1554 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1560 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
1562 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1563 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1569 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
1571 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1572 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1573 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1575 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
1576 slew-rate = <1>;
1577 drive-push-pull;
1578 bias-pull-up;
1582 slew-rate = <2>;
1583 drive-push-pull;
1584 bias-pull-up;
1588 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
1590 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1591 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1592 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1594 slew-rate = <1>;
1595 drive-push-pull;
1596 bias-pull-up;
1600 slew-rate = <2>;
1601 drive-push-pull;
1602 bias-pull-up;
1605 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
1606 slew-rate = <1>;
1607 drive-open-drain;
1608 bias-pull-up;
1612 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
1614 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1615 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1616 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
1619 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
1623 sdmmc3_b4_pins_b: sdmmc3-b4-1 {
1625 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1626 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1629 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
1630 slew-rate = <1>;
1631 drive-push-pull;
1632 bias-pull-up;
1636 slew-rate = <2>;
1637 drive-push-pull;
1638 bias-pull-up;
1642 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
1644 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1645 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1648 slew-rate = <1>;
1649 drive-push-pull;
1650 bias-pull-up;
1654 slew-rate = <2>;
1655 drive-push-pull;
1656 bias-pull-up;
1659 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
1660 slew-rate = <1>;
1661 drive-open-drain;
1662 bias-pull-up;
1666 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
1668 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1669 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1673 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
1677 spdifrx_pins_a: spdifrx-0 {
1680 bias-disable;
1684 spdifrx_sleep_pins_a: spdifrx-sleep-0 {
1690 spi2_pins_a: spi2-0 {
1694 bias-disable;
1695 drive-push-pull;
1696 slew-rate = <1>;
1701 bias-disable;
1705 spi4_pins_a: spi4-0 {
1709 bias-disable;
1710 drive-push-pull;
1711 slew-rate = <1>;
1715 bias-disable;
1719 stusb1600_pins_a: stusb1600-0 {
1722 bias-pull-up;
1726 uart4_pins_a: uart4-0 {
1729 bias-disable;
1730 drive-push-pull;
1731 slew-rate = <0>;
1735 bias-disable;
1739 uart4_idle_pins_a: uart4-idle-0 {
1745 bias-disable;
1749 uart4_sleep_pins_a: uart4-sleep-0 {
1756 uart4_pins_b: uart4-1 {
1759 bias-disable;
1760 drive-push-pull;
1761 slew-rate = <0>;
1765 bias-disable;
1769 uart4_pins_c: uart4-2 {
1772 bias-disable;
1773 drive-push-pull;
1774 slew-rate = <0>;
1778 bias-disable;
1782 uart7_pins_a: uart7-0 {
1785 bias-disable;
1786 drive-push-pull;
1787 slew-rate = <0>;
1792 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
1793 bias-disable;
1797 uart7_pins_b: uart7-1 {
1799 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
1800 bias-disable;
1801 drive-push-pull;
1802 slew-rate = <0>;
1805 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
1806 bias-disable;
1810 uart7_pins_c: uart7-2 {
1813 bias-disable;
1814 drive-push-pull;
1815 slew-rate = <0>;
1819 bias-disable;
1823 uart7_idle_pins_c: uart7-idle-2 {
1829 bias-disable;
1833 uart7_sleep_pins_c: uart7-sleep-2 {
1840 uart8_pins_a: uart8-0 {
1843 bias-disable;
1844 drive-push-pull;
1845 slew-rate = <0>;
1848 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
1849 bias-disable;
1853 uart8_rtscts_pins_a: uart8rtscts-0 {
1857 bias-disable;
1861 usart2_pins_a: usart2-0 {
1863 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
1865 bias-disable;
1866 drive-push-pull;
1867 slew-rate = <0>;
1872 bias-disable;
1876 usart2_sleep_pins_a: usart2-sleep-0 {
1878 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
1885 usart2_pins_b: usart2-1 {
1887 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
1888 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
1889 bias-disable;
1890 drive-push-pull;
1891 slew-rate = <0>;
1894 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
1896 bias-disable;
1900 usart2_sleep_pins_b: usart2-sleep-1 {
1902 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
1903 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
1904 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
1909 usart2_pins_c: usart2-2 {
1913 bias-disable;
1914 drive-push-pull;
1915 slew-rate = <3>;
1920 bias-disable;
1924 usart2_idle_pins_c: usart2-idle-2 {
1931 bias-disable;
1932 drive-push-pull;
1933 slew-rate = <3>;
1937 bias-disable;
1941 usart2_sleep_pins_c: usart2-sleep-2 {
1950 usart3_pins_a: usart3-0 {
1953 bias-disable;
1954 drive-push-pull;
1955 slew-rate = <0>;
1959 bias-disable;
1963 usart3_pins_b: usart3-1 {
1967 bias-disable;
1968 drive-push-pull;
1969 slew-rate = <0>;
1974 bias-disable;
1978 usart3_idle_pins_b: usart3-idle-1 {
1985 bias-disable;
1986 drive-push-pull;
1987 slew-rate = <0>;
1991 bias-disable;
1995 usart3_sleep_pins_b: usart3-sleep-1 {
2004 usart3_pins_c: usart3-2 {
2008 bias-disable;
2009 drive-push-pull;
2010 slew-rate = <0>;
2015 bias-disable;
2019 usart3_idle_pins_c: usart3-idle-2 {
2026 bias-disable;
2027 drive-push-pull;
2028 slew-rate = <0>;
2032 bias-disable;
2036 usart3_sleep_pins_c: usart3-sleep-2 {
2045 usbotg_hs_pins_a: usbotg-hs-0 {
2047 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
2051 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
2053 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
2054 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
2060 i2c2_pins_b2: i2c2-0 {
2062 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
2063 bias-disable;
2064 drive-open-drain;
2065 slew-rate = <0>;
2069 i2c2_sleep_pins_b2: i2c2-sleep-0 {
2071 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
2075 i2c4_pins_a: i2c4-0 {
2079 bias-disable;
2080 drive-open-drain;
2081 slew-rate = <0>;
2085 i2c4_sleep_pins_a: i2c4-sleep-0 {
2092 i2c6_pins_a: i2c6-0 {
2096 bias-disable;
2097 drive-open-drain;
2098 slew-rate = <0>;
2102 i2c6_sleep_pins_a: i2c6-sleep-0 {
2109 spi1_pins_a: spi1-0 {
2111 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
2113 bias-disable;
2114 drive-push-pull;
2115 slew-rate = <1>;
2120 bias-disable;