Lines Matching +full:use +full:- +full:ckin
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
24 * restriction, including without limitation the rights to use,
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
79 compatible = "st,stm32-timer";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "st,stm32-timers";
92 clock-names = "int";
96 compatible = "st,stm32-pwm";
97 #pwm-cells = <3>;
102 compatible = "st,stm32-timer-trigger";
109 compatible = "st,stm32-timer";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "st,stm32-timers";
122 clock-names = "int";
126 compatible = "st,stm32-pwm";
127 #pwm-cells = <3>;
132 compatible = "st,stm32-timer-trigger";
139 compatible = "st,stm32-timer";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "st,stm32-timers";
152 clock-names = "int";
156 compatible = "st,stm32-pwm";
157 #pwm-cells = <3>;
162 compatible = "st,stm32-timer-trigger";
169 compatible = "st,stm32-timer";
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "st,stm32-timers";
181 clock-names = "int";
185 compatible = "st,stm32-pwm";
186 #pwm-cells = <3>;
191 compatible = "st,stm32-timer-trigger";
198 compatible = "st,stm32-timer";
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "st,stm32-timers";
211 clock-names = "int";
215 compatible = "st,stm32-timer-trigger";
222 compatible = "st,stm32-timer";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "st,stm32-timers";
235 clock-names = "int";
239 compatible = "st,stm32-timer-trigger";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "st,stm32-timers";
251 clock-names = "int";
255 compatible = "st,stm32-pwm";
256 #pwm-cells = <3>;
261 compatible = "st,stm32-timer-trigger";
268 compatible = "st,stm32-timers";
271 clock-names = "int";
275 compatible = "st,stm32-pwm";
276 #pwm-cells = <3>;
282 compatible = "st,stm32-timers";
285 clock-names = "int";
289 compatible = "st,stm32-pwm";
290 #pwm-cells = <3>;
296 compatible = "st,stm32-rtc";
299 assigned-clocks = <&rcc 1 CLK_RTC>;
300 assigned-clock-parents = <&rcc 1 CLK_LSE>;
301 interrupt-parent = <&exti>;
308 compatible = "st,stm32f7-uart";
316 compatible = "st,stm32f7-uart";
324 compatible = "st,stm32f7-uart";
332 compatible = "st,stm32f7-uart";
340 compatible = "st,stm32f7-i2c";
346 #address-cells = <1>;
347 #size-cells = <0>;
352 compatible = "st,stm32f7-i2c";
358 #address-cells = <1>;
359 #size-cells = <0>;
364 compatible = "st,stm32f7-i2c";
370 #address-cells = <1>;
371 #size-cells = <0>;
376 compatible = "st,stm32f7-i2c";
382 #address-cells = <1>;
383 #size-cells = <0>;
388 compatible = "st,stm32-cec";
392 clock-names = "cec", "hdmi-cec";
397 compatible = "st,stm32f7-uart";
405 compatible = "st,stm32f7-uart";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "st,stm32-timers";
418 clock-names = "int";
422 compatible = "st,stm32-pwm";
423 #pwm-cells = <3>;
428 compatible = "st,stm32-timer-trigger";
435 #address-cells = <1>;
436 #size-cells = <0>;
437 compatible = "st,stm32-timers";
440 clock-names = "int";
444 compatible = "st,stm32-pwm";
445 #pwm-cells = <3>;
450 compatible = "st,stm32-timer-trigger";
457 compatible = "st,stm32f7-uart";
465 compatible = "st,stm32f7-uart";
474 arm,primecell-periphid = <0x00880180>;
477 clock-names = "apb_pclk";
479 max-frequency = <48000000>;
485 arm,primecell-periphid = <0x00880180>;
488 clock-names = "apb_pclk";
490 max-frequency = <48000000>;
495 compatible = "st,stm32-syscfg", "syscon";
499 exti: interrupt-controller@40013c00 {
500 compatible = "st,stm32-exti";
501 interrupt-controller;
502 #interrupt-cells = <2>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "st,stm32-timers";
513 clock-names = "int";
517 compatible = "st,stm32-pwm";
518 #pwm-cells = <3>;
523 compatible = "st,stm32-timer-trigger";
530 compatible = "st,stm32-timers";
533 clock-names = "int";
537 compatible = "st,stm32-pwm";
538 #pwm-cells = <3>;
544 compatible = "st,stm32-timers";
547 clock-names = "int";
551 compatible = "st,stm32-pwm";
552 #pwm-cells = <3>;
557 pwrcfg: power-config@40007000 {
558 compatible = "st,stm32-power-config", "syscon";
563 compatible = "st,stm32f7-crc";
570 #reset-cells = <1>;
571 #clock-cells = <2>;
572 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
576 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
577 assigned-clock-rates = <1000000>;
580 dma1: dma-controller@40026000 {
581 compatible = "st,stm32-dma";
592 #dma-cells = <4>;
596 dma2: dma-controller@40026400 {
597 compatible = "st,stm32-dma";
608 #dma-cells = <4>;
614 compatible = "st,stm32f7-hsotg";
618 clock-names = "otg";
619 g-rx-fifo-size = <256>;
620 g-np-tx-fifo-size = <32>;
621 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
626 compatible = "st,stm32f4x9-fsotg";
630 clock-names = "otg";