Lines Matching +full:stm32 +full:- +full:timers
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
84 compatible = "st,stm32f4-otp";
86 #address-cells = <1>;
87 #size-cells = <1>;
97 compatible = "st,stm32-timer";
104 timers2: timers@40000000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "st,stm32-timers";
110 clock-names = "int";
114 compatible = "st,stm32-pwm";
115 #pwm-cells = <3>;
120 compatible = "st,stm32-timer-trigger";
127 compatible = "st,stm32-timer";
134 timers3: timers@40000400 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "st,stm32-timers";
140 clock-names = "int";
144 compatible = "st,stm32-pwm";
145 #pwm-cells = <3>;
150 compatible = "st,stm32-timer-trigger";
157 compatible = "st,stm32-timer";
164 timers4: timers@40000800 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "st,stm32-timers";
170 clock-names = "int";
174 compatible = "st,stm32-pwm";
175 #pwm-cells = <3>;
180 compatible = "st,stm32-timer-trigger";
187 compatible = "st,stm32-timer";
193 timers5: timers@40000c00 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "st,stm32-timers";
199 clock-names = "int";
203 compatible = "st,stm32-pwm";
204 #pwm-cells = <3>;
209 compatible = "st,stm32-timer-trigger";
216 compatible = "st,stm32-timer";
223 timers6: timers@40001000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
229 clock-names = "int";
233 compatible = "st,stm32-timer-trigger";
240 compatible = "st,stm32-timer";
247 timers7: timers@40001400 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "st,stm32-timers";
253 clock-names = "int";
257 compatible = "st,stm32-timer-trigger";
263 timers12: timers@40001800 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "st,stm32-timers";
269 clock-names = "int";
273 compatible = "st,stm32-pwm";
274 #pwm-cells = <3>;
279 compatible = "st,stm32-timer-trigger";
285 timers13: timers@40001c00 {
286 compatible = "st,stm32-timers";
289 clock-names = "int";
293 compatible = "st,stm32-pwm";
294 #pwm-cells = <3>;
299 timers14: timers@40002000 {
300 compatible = "st,stm32-timers";
303 clock-names = "int";
307 compatible = "st,stm32-pwm";
308 #pwm-cells = <3>;
314 compatible = "st,stm32-rtc";
317 assigned-clocks = <&rcc 1 CLK_RTC>;
318 assigned-clock-parents = <&rcc 1 CLK_LSE>;
319 interrupt-parent = <&exti>;
326 compatible = "st,stm32-iwdg";
329 clock-names = "lsi";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 compatible = "st,stm32f4-spi";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "st,stm32f4-spi";
354 compatible = "st,stm32-uart";
362 compatible = "st,stm32-uart";
369 dma-names = "rx", "tx";
373 compatible = "st,stm32-uart";
381 compatible = "st,stm32-uart";
389 compatible = "st,stm32f4-i2c";
395 #address-cells = <1>;
396 #size-cells = <0>;
401 compatible = "st,stm32f4-i2c";
407 #address-cells = <1>;
408 #size-cells = <0>;
413 compatible = "st,stm32f4-dac-core";
417 clock-names = "pclk";
418 #address-cells = <1>;
419 #size-cells = <0>;
423 compatible = "st,stm32-dac";
424 #io-channel-cells = <1>;
430 compatible = "st,stm32-dac";
431 #io-channel-cells = <1>;
438 compatible = "st,stm32-uart";
446 compatible = "st,stm32-uart";
453 timers1: timers@40010000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "st,stm32-timers";
459 clock-names = "int";
463 compatible = "st,stm32-pwm";
464 #pwm-cells = <3>;
469 compatible = "st,stm32-timer-trigger";
475 timers8: timers@40010400 {
476 #address-cells = <1>;
477 #size-cells = <0>;
478 compatible = "st,stm32-timers";
481 clock-names = "int";
485 compatible = "st,stm32-pwm";
486 #pwm-cells = <3>;
491 compatible = "st,stm32-timer-trigger";
498 compatible = "st,stm32-uart";
505 dma-names = "rx", "tx";
509 compatible = "st,stm32-uart";
517 compatible = "st,stm32f4-adc-core";
521 clock-names = "adc";
522 interrupt-controller;
523 #interrupt-cells = <1>;
524 #address-cells = <1>;
525 #size-cells = <0>;
529 compatible = "st,stm32f4-adc";
530 #io-channel-cells = <1>;
533 interrupt-parent = <&adc>;
536 dma-names = "rx";
541 compatible = "st,stm32f4-adc";
542 #io-channel-cells = <1>;
545 interrupt-parent = <&adc>;
548 dma-names = "rx";
553 compatible = "st,stm32f4-adc";
554 #io-channel-cells = <1>;
557 interrupt-parent = <&adc>;
560 dma-names = "rx";
567 arm,primecell-periphid = <0x00880180>;
570 clock-names = "apb_pclk";
572 max-frequency = <48000000>;
577 #address-cells = <1>;
578 #size-cells = <0>;
579 compatible = "st,stm32f4-spi";
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "st,stm32f4-spi";
597 compatible = "st,stm32-syscfg", "syscon";
601 exti: interrupt-controller@40013c00 {
602 compatible = "st,stm32-exti";
603 interrupt-controller;
604 #interrupt-cells = <2>;
609 timers9: timers@40014000 {
610 #address-cells = <1>;
611 #size-cells = <0>;
612 compatible = "st,stm32-timers";
615 clock-names = "int";
619 compatible = "st,stm32-pwm";
620 #pwm-cells = <3>;
625 compatible = "st,stm32-timer-trigger";
631 timers10: timers@40014400 {
632 compatible = "st,stm32-timers";
635 clock-names = "int";
639 compatible = "st,stm32-pwm";
640 #pwm-cells = <3>;
645 timers11: timers@40014800 {
646 compatible = "st,stm32-timers";
649 clock-names = "int";
653 compatible = "st,stm32-pwm";
654 #pwm-cells = <3>;
660 #address-cells = <1>;
661 #size-cells = <0>;
662 compatible = "st,stm32f4-spi";
668 dma-names = "rx", "tx";
673 #address-cells = <1>;
674 #size-cells = <0>;
675 compatible = "st,stm32f4-spi";
682 pwrcfg: power-config@40007000 {
683 compatible = "st,stm32-power-config", "syscon";
687 ltdc: display-controller@40016800 {
688 compatible = "st,stm32-ltdc";
693 clock-names = "lcd";
698 compatible = "st,stm32f4-crc";
705 #reset-cells = <1>;
706 #clock-cells = <2>;
707 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
711 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
712 assigned-clock-rates = <1000000>;
715 dma1: dma-controller@40026000 {
716 compatible = "st,stm32-dma";
727 #dma-cells = <4>;
730 dma2: dma-controller@40026400 {
731 compatible = "st,stm32-dma";
742 #dma-cells = <4>;
747 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
749 reg-names = "stmmaceth";
751 interrupt-names = "macirq";
752 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
758 snps,mixed-burst;
767 clock-names = "otg";
772 compatible = "st,stm32f4x9-fsotg";
776 clock-names = "otg";
781 compatible = "st,stm32-dcmi";
786 clock-names = "mclk";
787 pinctrl-names = "default";
788 pinctrl-0 = <&dcmi_pins>;
790 dma-names = "tx";
795 compatible = "st,stm32-rng";