Lines Matching +full:0 +full:x400
58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 reg = <0x40000000 0x400>;
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
106 #size-cells = <0>;
108 reg = <0x40000000 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
128 reg = <0x40000400 0x400>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
136 #size-cells = <0>;
138 reg = <0x40000400 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
158 reg = <0x40000800 0x400>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
166 #size-cells = <0>;
168 reg = <0x40000800 0x400>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
188 reg = <0x40000c00 0x400>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
195 #size-cells = <0>;
197 reg = <0x40000C00 0x400>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
217 reg = <0x40001000 0x400>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
225 #size-cells = <0>;
227 reg = <0x40001000 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
241 reg = <0x40001400 0x400>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
249 #size-cells = <0>;
251 reg = <0x40001400 0x400>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
265 #size-cells = <0>;
267 reg = <0x40001800 0x400>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
287 reg = <0x40001C00 0x400>;
288 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
301 reg = <0x40002000 0x400>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
315 reg = <0x40002800 0x400>;
321 st,syscfg = <&pwrcfg 0x00 0x100>;
327 reg = <0x40003000 0x400>;
335 #size-cells = <0>;
337 reg = <0x40003800 0x400>;
339 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
345 #size-cells = <0>;
347 reg = <0x40003c00 0x400>;
349 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
355 reg = <0x40004400 0x400>;
357 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
363 reg = <0x40004800 0x400>;
365 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
367 dmas = <&dma1 1 4 0x400 0x0>,
368 <&dma1 3 4 0x400 0x0>;
374 reg = <0x40004c00 0x400>;
376 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
382 reg = <0x40005000 0x400>;
384 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
390 reg = <0x40005400 0x400>;
394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
396 #size-cells = <0>;
402 reg = <0x40005c00 0x400>;
406 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
408 #size-cells = <0>;
414 reg = <0x40007400 0x400>;
416 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
419 #size-cells = <0>;
439 reg = <0x40007800 0x400>;
441 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
447 reg = <0x40007c00 0x400>;
449 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
455 #size-cells = <0>;
457 reg = <0x40010000 0x400>;
458 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
468 timer@0 {
470 reg = <0>;
477 #size-cells = <0>;
479 reg = <0x40010400 0x400>;
480 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
499 reg = <0x40011000 0x400>;
501 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
503 dmas = <&dma2 2 4 0x400 0x0>,
504 <&dma2 7 4 0x400 0x0>;
510 reg = <0x40011400 0x400>;
512 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
518 reg = <0x40012000 0x400>;
520 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
525 #size-cells = <0>;
528 adc1: adc@0 {
531 reg = <0x0>;
532 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
534 interrupts = <0>;
535 dmas = <&dma2 0 0 0x400 0x0>;
543 reg = <0x100>;
544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
547 dmas = <&dma2 3 1 0x400 0x0>;
555 reg = <0x200>;
556 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
559 dmas = <&dma2 1 2 0x400 0x0>;
567 arm,primecell-periphid = <0x00880180>;
568 reg = <0x40012c00 0x400>;
569 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
578 #size-cells = <0>;
580 reg = <0x40013000 0x400>;
582 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
588 #size-cells = <0>;
590 reg = <0x40013400 0x400>;
592 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
598 reg = <0x40013800 0x400>;
605 reg = <0x40013C00 0x400>;
611 #size-cells = <0>;
613 reg = <0x40014000 0x400>;
614 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
633 reg = <0x40014400 0x400>;
634 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
647 reg = <0x40014800 0x400>;
648 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
661 #size-cells = <0>;
663 reg = <0x40015000 0x400>;
665 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
666 dmas = <&dma2 3 2 0x400 0x0>,
667 <&dma2 4 2 0x400 0x0>;
674 #size-cells = <0>;
676 reg = <0x40015400 0x400>;
678 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
684 reg = <0x40007000 0x400>;
689 reg = <0x40016800 0x200>;
699 reg = <0x40023000 0x400>;
700 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
708 reg = <0x40023800 0x400>;
717 reg = <0x40026000 0x400>;
726 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
732 reg = <0x40026400 0x400>;
741 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
748 reg = <0x40028000 0x8000>;
753 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
754 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
755 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
756 st,syscon = <&syscfg 0x4>;
764 reg = <0x40040000 0x40000>;
766 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
773 reg = <0x50000000 0x40000>;
775 clocks = <&rcc 0 39>;
782 reg = <0x50050000 0x400>;
785 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
788 pinctrl-0 = <&dcmi_pins>;
789 dmas = <&dma2 1 1 0x414 0x3>;
796 reg = <0x50060800 0x400>;
797 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;