Lines Matching +full:i2c +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9-pmu";
34 interrupt-parent = <&intc>;
36 interrupt-affinity = <&cpu0>, <&cpu1>;
42 compatible = "arm,cortex-a9-gic";
43 #interrupt-cells = <3>;
44 interrupt-controller;
50 #address-cells = <1>;
51 #size-cells = <1>;
52 compatible = "simple-bus";
54 interrupt-parent = <&intc>;
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
75 #dma-cells = <1>;
76 #dma-channels = <8>;
77 #dma-requests = <32>;
79 clock-names = "apb_pclk";
81 reset-names = "dma", "dma-ocp";
86 #address-cells = <0x1>;
87 #size-cells = <0x1>;
89 compatible = "fpga-region";
90 fpga-mgr = <&fpga_mgr>;
94 compatible = "altr,clk-mgr";
98 #address-cells = <1>;
99 #size-cells = <0>;
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
122 #address-cells = <1>;
123 #size-cells = <0>;
124 #clock-cells = <0>;
125 compatible = "altr,socfpga-a10-pll-clock";
131 #clock-cells = <0>;
132 compatible = "altr,socfpga-a10-perip-clk";
134 div-reg = <0x140 0 11>;
138 #clock-cells = <0>;
139 compatible = "altr,socfpga-a10-perip-clk";
141 div-reg = <0x144 0 11>;
145 #clock-cells = <0>;
146 compatible = "altr,socfpga-a10-perip-clk";
152 #clock-cells = <0>;
153 compatible = "altr,socfpga-a10-perip-clk";
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-a10-perip-clk";
166 #clock-cells = <0>;
167 compatible = "altr,socfpga-a10-perip-clk";
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-a10-perip-clk"
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-a10-perip-clk";
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-a10-perip-clk";
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-a10-perip-clk";
202 #clock-cells = <0>;
203 compatible = "altr,socfpga-a10-perip-clk";
210 #address-cells = <1>;
211 #size-cells = <0>;
212 #clock-cells = <0>;
213 compatible = "altr,socfpga-a10-pll-clock";
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-a10-perip-clk";
222 div-reg = <0x140 16 11>;
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-a10-perip-clk";
229 div-reg = <0x144 16 11>;
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-a10-perip-clk";
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-a10-perip-clk";
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-a10-perip-clk";
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-a10-perip-clk";
261 #clock-cells = <0>;
262 compatible = "altr,socfpga-a10-perip-clk";
268 #clock-cells = <0>;
269 compatible = "altr,socfpga-a10-perip-clk";
275 #clock-cells = <0>;
276 compatible = "altr,socfpga-a10-perip-clk";
282 #clock-cells = <0>;
283 compatible = "altr,socfpga-a10-perip-clk";
290 #clock-cells = <0>;
291 compatible = "altr,socfpga-a10-perip-clk";
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-a10-perip-clk";
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-a10-perip-clk";
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-a10-perip-clk";
322 fixed-divider = <4>;
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-a10-perip-clk";
330 fixed-divider = <4>;
334 #clock-cells = <0>;
335 compatible = "altr,socfpga-a10-gate-clk";
337 div-reg = <0xA8 0 2>;
338 clk-gate = <0x48 1>;
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-a10-gate-clk";
345 div-reg = <0xA8 8 2>;
346 clk-gate = <0x48 2>;
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-a10-gate-clk";
353 div-reg = <0xA8 16 2>;
354 clk-gate = <0x48 3>;
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-a10-gate-clk";
361 fixed-divider = <4>;
362 clk-gate = <0x48 0>;
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-a10-gate-clk";
369 clk-gate = <0xC8 5>;
370 clk-phase = <0 135>;
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-a10-gate-clk";
377 clk-gate = <0xC8 11>;
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-a10-gate-clk";
384 clk-gate = <0xC8 10>;
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-a10-gate-clk";
391 clk-gate = <0xC8 10>;
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-a10-gate-clk";
398 fixed-divider = <4>;
399 clk-gate = <0xC8 10>;
403 #clock-cells = <0>;
404 compatible = "altr,socfpga-a10-gate-clk";
406 clk-gate = <0xC8 9>;
410 #clock-cells = <0>;
411 compatible = "altr,socfpga-a10-gate-clk";
413 clk-gate = <0xC8 8>;
417 #clock-cells = <0>;
418 compatible = "altr,socfpga-a10-gate-clk";
420 clk-gate = <0xC8 6>;
425 socfpga_axi_setup: stmmac-axi-config {
432 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
433 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
436 interrupt-names = "macirq";
438 mac-address = [00 00 00 00 00 00];
439 snps,multicast-filter-bins = <256>;
440 snps,perfect-filter-entries = <128>;
441 tx-fifo-depth = <4096>;
442 rx-fifo-depth = <16384>;
444 clock-names = "stmmaceth", "ptp_ref";
446 reset-names = "stmmaceth", "stmmaceth-ocp";
447 snps,axi-config = <&socfpga_axi_setup>;
452 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
453 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
456 interrupt-names = "macirq";
458 mac-address = [00 00 00 00 00 00];
459 snps,multicast-filter-bins = <256>;
460 snps,perfect-filter-entries = <128>;
461 tx-fifo-depth = <4096>;
462 rx-fifo-depth = <16384>;
464 clock-names = "stmmaceth", "ptp_ref";
466 reset-names = "stmmaceth", "stmmaceth-ocp";
467 snps,axi-config = <&socfpga_axi_setup>;
472 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
473 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
476 interrupt-names = "macirq";
478 mac-address = [00 00 00 00 00 00];
479 snps,multicast-filter-bins = <256>;
480 snps,perfect-filter-entries = <128>;
481 tx-fifo-depth = <4096>;
482 rx-fifo-depth = <16384>;
484 clock-names = "stmmaceth", "ptp_ref";
486 reset-names = "stmmaceth", "stmmaceth-ocp";
487 snps,axi-config = <&socfpga_axi_setup>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 compatible = "snps,dw-apb-gpio";
499 porta: gpio-controller@0 {
500 compatible = "snps,dw-apb-gpio-port";
501 gpio-controller;
502 #gpio-cells = <2>;
503 snps,nr-gpios = <29>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 compatible = "snps,dw-apb-gpio";
519 portb: gpio-controller@0 {
520 compatible = "snps,dw-apb-gpio-port";
521 gpio-controller;
522 #gpio-cells = <2>;
523 snps,nr-gpios = <29>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "snps,dw-apb-gpio";
539 portc: gpio-controller@0 {
540 compatible = "snps,dw-apb-gpio-port";
541 gpio-controller;
542 #gpio-cells = <2>;
543 snps,nr-gpios = <27>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
551 fpga_mgr: fpga-mgr@ffd03000 {
552 compatible = "altr,socfpga-a10-fpga-mgr";
557 reset-names = "fpgamgr";
560 i2c0: i2c@ffc02200 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "snps,designware-i2c";
571 i2c1: i2c@ffc02300 {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 compatible = "snps,designware-i2c";
582 i2c2: i2c@ffc02400 {
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "snps,designware-i2c";
593 i2c3: i2c@ffc02500 {
594 #address-cells = <1>;
595 #size-cells = <0>;
596 compatible = "snps,designware-i2c";
604 i2c4: i2c@ffc02600 {
605 #address-cells = <1>;
606 #size-cells = <0>;
607 compatible = "snps,designware-i2c";
616 compatible = "snps,dw-apb-ssi";
617 #address-cells = <1>;
618 #size-cells = <0>;
621 num-cs = <4>;
625 reset-names = "spi";
630 compatible = "snps,dw-apb-ssi";
631 #address-cells = <1>;
632 #size-cells = <0>;
635 num-cs = <4>;
637 tx-dma-channel = <&pdma 16>;
638 rx-dma-channel = <&pdma 17>;
641 reset-names = "spi";
646 compatible = "altr,sdr-ctl", "syscon";
650 L2: cache-controller@fffff000 {
651 compatible = "arm,pl310-cache";
654 cache-unified;
655 cache-level = <2>;
656 prefetch-data = <1>;
657 prefetch-instr = <1>;
658 arm,shared-override;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 compatible = "altr,socfpga-dw-mshc";
667 fifo-depth = <0x400>;
669 clock-names = "biu", "ciu";
675 #address-cells = <1>;
676 #size-cells = <0>;
677 compatible = "altr,socfpga-denali-nand";
680 reg-names = "nand_data", "denali_reg";
683 clock-names = "nand", "nand_x", "ecc";
689 compatible = "mmio-sram";
694 compatible = "altr,socfpga-a10-ecc-manager";
695 altr,sysmgr-syscon = <&sysmgr>;
696 #address-cells = <1>;
697 #size-cells = <1>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
705 compatible = "altr,sdram-edac-a10";
706 altr,sdr-syscon = <&sdr>;
711 l2-ecc@ffd06010 {
712 compatible = "altr,socfpga-a10-l2-ecc";
718 ocram-ecc@ff8c3000 {
719 compatible = "altr,socfpga-a10-ocram-ecc";
725 emac0-rx-ecc@ff8c0800 {
726 compatible = "altr,socfpga-eth-mac-ecc";
728 altr,ecc-parent = <&gmac0>;
733 emac0-tx-ecc@ff8c0c00 {
734 compatible = "altr,socfpga-eth-mac-ecc";
736 altr,ecc-parent = <&gmac0>;
741 dma-ecc@ff8c8000 {
742 compatible = "altr,socfpga-dma-ecc";
744 altr,ecc-parent = <&pdma>;
749 usb0-ecc@ff8c8800 {
750 compatible = "altr,socfpga-usb-ecc";
752 altr,ecc-parent = <&usb0>;
759 compatible = "cdns,qspi-nor";
760 #address-cells = <1>;
761 #size-cells = <0>;
765 cdns,fifo-depth = <128>;
766 cdns,fifo-width = <4>;
767 cdns,trigger-address = <0x00000000>;
770 reset-names = "qspi", "qspi-ocp";
775 #reset-cells = <1>;
776 compatible = "altr,rst-mgr";
778 altr,modrst-offset = <0x20>;
781 scu: snoop-control-unit@ffffc000 {
782 compatible = "arm,cortex-a9-scu";
787 compatible = "altr,sys-mgr", "syscon";
789 cpu1-start-addr = <0xffd06230>;
794 compatible = "arm,cortex-a9-twd-timer";
801 compatible = "snps,dw-apb-timer";
805 clock-names = "timer";
807 reset-names = "timer";
811 compatible = "snps,dw-apb-timer";
815 clock-names = "timer";
817 reset-names = "timer";
821 compatible = "snps,dw-apb-timer";
825 clock-names = "timer";
827 reset-names = "timer";
831 compatible = "snps,dw-apb-timer";
835 clock-names = "timer";
837 reset-names = "timer";
841 compatible = "snps,dw-apb-uart";
844 reg-shift = <2>;
845 reg-io-width = <4>;
852 compatible = "snps,dw-apb-uart";
855 reg-shift = <2>;
856 reg-io-width = <4>;
863 #phy-cells = <0>;
864 compatible = "usb-nop-xceiv";
873 clock-names = "otg";
875 reset-names = "dwc2";
877 phy-names = "usb2-phy";
886 clock-names = "otg";
888 reset-names = "dwc2";
890 phy-names = "usb2-phy";
895 compatible = "snps,dw-wdt";
904 compatible = "snps,dw-wdt";