Lines Matching +full:0 +full:xffd04000
15 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
35 interrupts = <0 124 4>, <0 125 4>;
37 reg = <0xff111000 0x1000>,
38 <0xff113000 0x1000>;
45 reg = <0xffffd000 0x1000>,
46 <0xffffc100 0x100>;
65 reg = <0xffda1000 0x1000>;
66 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
67 <0 84 IRQ_TYPE_LEVEL_HIGH>,
68 <0 85 IRQ_TYPE_LEVEL_HIGH>,
69 <0 86 IRQ_TYPE_LEVEL_HIGH>,
70 <0 87 IRQ_TYPE_LEVEL_HIGH>,
71 <0 88 IRQ_TYPE_LEVEL_HIGH>,
72 <0 89 IRQ_TYPE_LEVEL_HIGH>,
73 <0 90 IRQ_TYPE_LEVEL_HIGH>,
74 <0 91 IRQ_TYPE_LEVEL_HIGH>;
86 #address-cells = <0x1>;
87 #size-cells = <0x1>;
95 reg = <0xffd04000 0x1000>;
99 #size-cells = <0>;
102 #clock-cells = <0>;
107 #clock-cells = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
123 #size-cells = <0>;
124 #clock-cells = <0>;
128 reg = <0x40>;
131 #clock-cells = <0>;
134 div-reg = <0x140 0 11>;
138 #clock-cells = <0>;
141 div-reg = <0x144 0 11>;
145 #clock-cells = <0>;
148 reg = <0x68>;
152 #clock-cells = <0>;
155 reg = <0x6C>;
159 #clock-cells = <0>;
162 reg = <0x70>;
166 #clock-cells = <0>;
169 reg = <0x74>;
173 #clock-cells = <0>;
177 reg = <0x78>;
181 #clock-cells = <0>;
184 reg = <0x7C>;
188 #clock-cells = <0>;
191 reg = <0x80>;
195 #clock-cells = <0>;
198 reg = <0x84>;
202 #clock-cells = <0>;
205 reg = <0x9C>;
211 #size-cells = <0>;
212 #clock-cells = <0>;
216 reg = <0xC0>;
219 #clock-cells = <0>;
222 div-reg = <0x140 16 11>;
226 #clock-cells = <0>;
229 div-reg = <0x144 16 11>;
233 #clock-cells = <0>;
236 reg = <0xE8>;
240 #clock-cells = <0>;
243 reg = <0xEC>;
247 #clock-cells = <0>;
250 reg = <0xF0>;
254 #clock-cells = <0>;
257 reg = <0xF4>;
261 #clock-cells = <0>;
264 reg = <0xF8>;
268 #clock-cells = <0>;
271 reg = <0xFC>;
275 #clock-cells = <0>;
278 reg = <0x100>;
282 #clock-cells = <0>;
285 reg = <0x104>;
290 #clock-cells = <0>;
295 reg = <0x60>;
299 #clock-cells = <0>;
304 reg = <0x64>;
308 #clock-cells = <0>;
313 reg = <0x104>;
317 #clock-cells = <0>;
323 reg = <0xF8>;
327 #clock-cells = <0>;
334 #clock-cells = <0>;
337 div-reg = <0xA8 0 2>;
338 clk-gate = <0x48 1>;
342 #clock-cells = <0>;
345 div-reg = <0xA8 8 2>;
346 clk-gate = <0x48 2>;
350 #clock-cells = <0>;
353 div-reg = <0xA8 16 2>;
354 clk-gate = <0x48 3>;
358 #clock-cells = <0>;
362 clk-gate = <0x48 0>;
366 #clock-cells = <0>;
369 clk-gate = <0xC8 5>;
370 clk-phase = <0 135>;
374 #clock-cells = <0>;
377 clk-gate = <0xC8 11>;
381 #clock-cells = <0>;
384 clk-gate = <0xC8 10>;
388 #clock-cells = <0>;
391 clk-gate = <0xC8 10>;
395 #clock-cells = <0>;
399 clk-gate = <0xC8 10>;
403 #clock-cells = <0>;
406 clk-gate = <0xC8 9>;
410 #clock-cells = <0>;
413 clk-gate = <0xC8 8>;
417 #clock-cells = <0>;
420 clk-gate = <0xC8 6>;
426 snps,wr_osr_lmt = <0xf>;
427 snps,rd_osr_lmt = <0xf>;
428 snps,blen = <0 0 0 0 16 0 0>;
433 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
434 reg = <0xff800000 0x2000>;
435 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
453 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
454 reg = <0xff802000 0x2000>;
455 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
473 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
474 reg = <0xff804000 0x2000>;
475 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
493 #size-cells = <0>;
495 reg = <0xffc02900 0x100>;
499 porta: gpio-controller@0 {
504 reg = <0>;
507 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
513 #size-cells = <0>;
515 reg = <0xffc02a00 0x100>;
519 portb: gpio-controller@0 {
524 reg = <0>;
527 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
533 #size-cells = <0>;
535 reg = <0xffc02b00 0x100>;
539 portc: gpio-controller@0 {
544 reg = <0>;
547 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
553 reg = <0xffd03000 0x100
554 0xffcfe400 0x20>;
562 #size-cells = <0>;
564 reg = <0xffc02200 0x100>;
565 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
573 #size-cells = <0>;
575 reg = <0xffc02300 0x100>;
576 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
584 #size-cells = <0>;
586 reg = <0xffc02400 0x100>;
587 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
595 #size-cells = <0>;
597 reg = <0xffc02500 0x100>;
598 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
606 #size-cells = <0>;
608 reg = <0xffc02600 0x100>;
609 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
618 #size-cells = <0>;
619 reg = <0xffda4000 0x100>;
620 interrupts = <0 101 4>;
632 #size-cells = <0>;
633 reg = <0xffda5000 0x100>;
634 interrupts = <0 102 4>;
647 reg = <0xffcfb100 0x80>;
652 reg = <0xfffff000 0x1000>;
653 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
663 #size-cells = <0>;
665 reg = <0xff808000 0x1000>;
666 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
667 fifo-depth = <0x400>;
676 #size-cells = <0>;
678 reg = <0xffb90000 0x72000>,
679 <0xffb80000 0x10000>;
681 interrupts = <0 99 4>;
690 reg = <0xffe00000 0x40000>;
698 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
699 <0 0 IRQ_TYPE_LEVEL_HIGH>;
713 reg = <0xffd06010 0x4>;
714 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
720 reg = <0xff8c3000 0x400>;
727 reg = <0xff8c0800 0x400>;
735 reg = <0xff8c0c00 0x400>;
743 reg = <0xff8c8000 0x400>;
751 reg = <0xff8c8800 0x400>;
761 #size-cells = <0>;
762 reg = <0xff809000 0x100>,
763 <0xffa00000 0x100000>;
764 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
767 cdns,trigger-address = <0x00000000>;
777 reg = <0xffd05000 0x100>;
778 altr,modrst-offset = <0x20>;
783 reg = <0xffffc000 0x100>;
788 reg = <0xffd06000 0x300>;
789 cpu1-start-addr = <0xffd06230>;
795 reg = <0xffffc600 0x100>;
796 interrupts = <1 13 0xf01>;
802 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0xffc02700 0x100>;
812 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
813 reg = <0xffc02800 0x100>;
822 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
823 reg = <0xffd00000 0x100>;
832 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
833 reg = <0xffd00100 0x100>;
842 reg = <0xffc02000 0x100>;
843 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
853 reg = <0xffc02100 0x100>;
854 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
863 #phy-cells = <0>;
870 reg = <0xffb00000 0xffff>;
871 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
883 reg = <0xffb40000 0xffff>;
884 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
896 reg = <0xffd00200 0x100>;
897 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
905 reg = <0xffd00300 0x100>;
906 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;