Lines Matching +full:0 +full:xfffffe00
45 #size-cells = <0>;
46 cpu@0 {
49 reg = <0x0>;
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
60 reg = <0x20000000 0x8000000>;
66 #clock-cells = <0>;
67 clock-frequency = <0>;
72 #clock-cells = <0>;
73 clock-frequency = <0>;
78 #clock-cells = <0>;
85 reg = <0x00300000 0x20000>;
88 ranges = <0 0x00300000 0x20000>;
105 reg = <0xf0000000 0x600>;
106 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
107 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
110 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
113 #size-cells = <0>;
120 #size-cells = <0>;
122 reg = <0xf0004000 0x100>;
128 pinctrl-0 = <&pinctrl_spi0>;
136 reg = <0xf0008000 0x4000>;
142 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
151 #size-cells = <0>;
152 reg = <0xf0010000 0x100>;
153 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
160 reg = <0xf0014000 0x4000>;
166 pinctrl-0 = <&pinctrl_i2c0>;
171 #size-cells = <0>;
178 reg = <0xf0018000 0x4000>;
184 pinctrl-0 = <&pinctrl_i2c1>;
189 #size-cells = <0>;
196 reg = <0xf001c000 0x100>;
202 pinctrl-0 = <&pinctrl_usart0>;
210 reg = <0xf0020000 0x100>;
216 pinctrl-0 = <&pinctrl_usart1>;
224 reg = <0xf0024000 0x100>;
227 pinctrl-0 = <&pinctrl_uart0>;
235 reg = <0xf002c000 0x300>;
244 reg = <0xf0034000 0x4000>;
247 pinctrl-0 = <&pinctrl_isi_data_0_7>;
253 #size-cells = <0>;
259 reg = <0xf0038000 0x60>;
264 reg = <0xf8000000 0x600>;
265 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
266 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
269 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
272 #size-cells = <0>;
279 #size-cells = <0>;
281 reg = <0xf8008000 0x100>;
287 pinctrl-0 = <&pinctrl_spi1>;
295 reg = <0xf800c000 0x4000>;
301 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
309 reg = <0xf8018000 0x100>;
312 pinctrl-0 = <
330 atmel,adc-channels-used = <0xfff>;
340 reg = <0xf801c000 0x4000>;
346 pinctrl-0 = <&pinctrl_i2c2>;
351 #size-cells = <0>;
358 reg = <0xf8020000 0x100>;
364 pinctrl-0 = <&pinctrl_usart2>;
372 reg = <0xf8024000 0x100>;
378 pinctrl-0 = <&pinctrl_usart3>;
386 reg = <0xf8034000 0x100>;
387 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
396 reg = <0xf8038000 0x100>;
397 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
407 reg = <0xf803c000 0x100>;
408 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
418 reg = <0xf8040000 0x100>;
419 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
425 reg = <0xffffc000 0x1000>;
434 reg = <0xffffc070 0x490>,
435 <0xffffc500 0x100>;
441 reg = <0xffffe600 0x200>;
442 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
450 reg = <0xffffe800 0x200>;
451 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
459 reg = <0xffffea00 0x200>;
466 reg = <0xffffee00 0x200>;
472 pinctrl-0 = <&pinctrl_dbgu>;
482 reg = <0xfffff000 0x200>;
490 ranges = <0xfffff200 0xfffff200 0xa00>;
493 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
494 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
495 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
496 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
497 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
557 pinctrl_dbgu: dbgu-0 {
565 pinctrl_ebi_addr: ebi-addr-0 {
598 pinctrl_ebi_cs0: ebi-cs0-0 {
603 pinctrl_ebi_cs1: ebi-cs1-0 {
608 pinctrl_ebi_cs2: ebi-cs2-0 {
613 pinctrl_ebi_nwait: ebi-nwait-0 {
618 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
625 pinctrl_i2c0: i2c0-0 {
639 pinctrl_i2c1: i2c1-0 {
653 pinctrl_i2c2: i2c2-0 {
667 pinctrl_isi_data_0_7: isi-0-data-0-7 {
682 pinctrl_isi_data_8_9: isi-0-data-8-9 {
688 pinctrl_isi_data_10_11: isi-0-data-10-11 {
699 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
733 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
741 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
747 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
749 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
758 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
770 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
783 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
791 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
800 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
808 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
819 pinctrl_spi0: spi0-0 {
828 pinctrl_spi1: spi1-0 {
869 pinctrl_uart0: uart0-0 {
877 pinctrl_uart1: uart1-0 {
885 pinctrl_usart0: usart0-0 {
891 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
899 pinctrl_usart1: usart1-0 {
905 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
913 pinctrl_usart2: usart2-0 {
919 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
927 pinctrl_usart3: usart3-0 {
933 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
943 reg = <0xfffff200 0x100>;
954 reg = <0xfffff400 0x100>;
965 reg = <0xfffff600 0x100>;
976 reg = <0xfffff800 0x100>;
987 reg = <0xfffffa00 0x100>;
999 reg = <0xfffffc00 0x120>;
1008 reg = <0xfffffe00 0x10>;
1014 reg = <0xfffffe10 0x10>;
1020 reg = <0xfffffe30 0xf>;
1027 reg = <0xfffffe40 0x10>;
1038 reg = <0xfffffe50 0x4>;
1040 #clock-cells = <0>;
1045 reg = <0xfffffeb0 0x30>;
1054 reg = <0x200000 0x2400>;
1057 ranges = <0 0x200000 0x2400>;
1062 reg = <0x00500000 0x100000
1063 0xf8030000 0x4000>;
1072 reg = <0x00600000 0x100000>;
1081 reg = <0x00700000 0x100000>;
1093 reg = <0x10000000 0x10000000
1094 0x40000000 0x30000000>;
1095 ranges = <0x0 0x0 0x10000000 0x10000000
1096 0x1 0x0 0x40000000 0x10000000
1097 0x2 0x0 0x50000000 0x10000000
1098 0x3 0x0 0x60000000 0x10000000>;
1116 reg = <0x70000000 0x8000000>;