Lines Matching refs:clocks
82 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
94 clocks: clock-controller@e0100000 { label
98 clocks = <&xxti>, <&xusbxti>;
125 clocks = <&clocks CLK_PDMA0>;
137 clocks = <&clocks CLK_PDMA1>;
149 clocks = <&clocks CLK_TSADC>;
162 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
178 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
192 clocks = <&clocks CLK_KEYIF>;
202 clocks = <&clocks CLK_I2C0>;
216 clocks = <&clocks CLK_I2C2>;
231 clocks = <&clocks DOUT_HCLKP>, <&xxti>,
232 <&clocks FOUT_EPLL>,
233 <&clocks SCLK_AUDIO0>;
247 clocks = <&clk_audss CLK_I2S>,
265 clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>;
280 clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
293 clocks = <&clocks CLK_PWM>;
303 clocks = <&clocks CLK_WDT>;
311 clocks = <&clocks CLK_RTC>;
323 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
324 <&clocks SCLK_UART0>;
335 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
336 <&clocks SCLK_UART1>;
347 clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
348 <&clocks SCLK_UART2>;
359 clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>,
360 <&clocks SCLK_UART3>;
370 clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>,
371 <&clocks SCLK_MMC0>;
381 clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>,
382 <&clocks SCLK_MMC1>;
392 clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>,
393 <&clocks SCLK_MMC2>;
403 clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>,
404 <&clocks SCLK_MMC3>;
413 clocks = <&clocks CLK_USB_OTG>;
424 clocks = <&clocks CLK_USB_OTG>, <&xusbxti>;
435 clocks = <&clocks CLK_USB_HOST>;
452 clocks = <&clocks CLK_USB_HOST>;
469 clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>;
507 clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>;
527 clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>;
536 clocks = <&clocks CLK_MDMA>;
548 clocks = <&clocks CLK_ROTATOR>;
557 clocks = <&clocks CLK_I2C1>;
570 clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>;
583 clocks = <&clocks CLK_CSIS>,
584 <&clocks SCLK_CSIS>;
598 clocks = <&clocks CLK_FIMC0>,
599 <&clocks SCLK_FIMC0>;
612 clocks = <&clocks CLK_FIMC1>,
613 <&clocks SCLK_FIMC1>;
628 clocks = <&clocks CLK_FIMC2>,
629 <&clocks SCLK_FIMC2>;
644 clocks = <&clocks CLK_JPEG>;