Lines Matching +full:rx +full:- +full:sample +full:- +full:delay +full:- +full:ns
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a7";
35 clock-latency = <40000>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
44 compatible = "operating-points-v2";
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
74 compatible = "arm,armv7-timer";
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
98 #dma-cells = <1>;
99 arm,pl330-broken-no-flushp;
100 arm,pl330-periph-burst;
102 clock-names = "apb_pclk";
107 compatible = "mmio-sram";
109 #address-cells = <1>;
110 #size-cells = <1>;
115 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
118 reg-shift = <2>;
119 reg-io-width = <4>;
120 clock-frequency = <24000000>;
122 clock-names = "baudclk", "apb_pclk";
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 clock-frequency = <24000000>;
137 clock-names = "baudclk", "apb_pclk";
139 pinctrl-names = "default";
140 pinctrl-0 = <&uart1_xfer>;
145 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
148 reg-shift = <2>;
149 reg-io-width = <4>;
150 clock-frequency = <24000000>;
152 clock-names = "baudclk", "apb_pclk";
154 pinctrl-names = "default";
155 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
160 compatible = "rockchip,rv1108-i2c";
163 #address-cells = <1>;
164 #size-cells = <0>;
166 clock-names = "i2c", "pclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&i2c1_xfer>;
174 compatible = "rockchip,rv1108-i2c";
177 #address-cells = <1>;
178 #size-cells = <0>;
180 clock-names = "i2c", "pclk";
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2c2m1_xfer>;
188 compatible = "rockchip,rv1108-i2c";
191 #address-cells = <1>;
192 #size-cells = <0>;
194 clock-names = "i2c", "pclk";
195 pinctrl-names = "default";
196 pinctrl-0 = <&i2c3_xfer>;
202 compatible = "rockchip,rv1108-spi";
206 clock-names = "spiclk", "apb_pclk";
208 dma-names = "tx", "rx";
209 #address-cells = <1>;
210 #size-cells = <0>;
215 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
219 clock-names = "pwm", "pclk";
220 pinctrl-names = "default";
221 pinctrl-0 = <&pwm4_pin>;
222 #pwm-cells = <3>;
227 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
231 clock-names = "pwm", "pclk";
232 pinctrl-names = "default";
233 pinctrl-0 = <&pwm5_pin>;
234 #pwm-cells = <3>;
239 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
243 clock-names = "pwm", "pclk";
244 pinctrl-names = "default";
245 pinctrl-0 = <&pwm6_pin>;
246 #pwm-cells = <3>;
251 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
255 clock-names = "pwm", "pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pwm7_pin>;
258 #pwm-cells = <3>;
263 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
265 #address-cells = <1>;
266 #size-cells = <1>;
268 io_domains: io-domains {
269 compatible = "rockchip,rv1108-io-voltage-domain";
274 compatible = "rockchip,rv1108-usb2phy";
277 clock-names = "phyclk";
278 #clock-cells = <0>;
279 clock-output-names = "usbphy";
283 u2phy_otg: otg-port {
285 interrupt-names = "otg-mux";
286 #phy-cells = <0>;
290 u2phy_host: host-port {
292 interrupt-names = "linestate";
293 #phy-cells = <0>;
300 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
304 clock-names = "timer", "pclk";
308 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
315 thermal-zones {
316 soc_thermal: soc-thermal {
317 polling-delay-passive = <20>;
318 polling-delay = <1000>;
319 sustainable-power = <50>;
320 thermal-sensors = <&tsadc 0>;
323 threshold: trip-point0 {
328 target: trip-point1 {
333 soc_crit: soc-crit {
340 cooling-maps {
343 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
351 compatible = "rockchip,rv1108-tsadc";
354 assigned-clocks = <&cru SCLK_TSADC>;
355 assigned-clock-rates = <750000>;
357 clock-names = "tsadc", "apb_pclk";
358 pinctrl-names = "init", "default", "sleep";
359 pinctrl-0 = <&otp_pin>;
360 pinctrl-1 = <&otp_out>;
361 pinctrl-2 = <&otp_pin>;
363 reset-names = "tsadc-apb";
364 rockchip,hw-tshut-temp = <120000>;
365 #thermal-sensor-cells = <1>;
370 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
373 #io-channel-cells = <1>;
375 clock-names = "saradc", "apb_pclk";
380 compatible = "rockchip,rv1108-i2c";
383 #address-cells = <1>;
384 #size-cells = <0>;
386 clock-names = "i2c", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c0_xfer>;
394 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
398 clock-names = "pwm", "pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm0_pin>;
401 #pwm-cells = <3>;
406 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
410 clock-names = "pwm", "pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&pwm1_pin>;
413 #pwm-cells = <3>;
418 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
422 clock-names = "pwm", "pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm2_pin>;
425 #pwm-cells = <3>;
430 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm3_pin>;
437 #pwm-cells = <3>;
442 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
445 pmu_io_domains: io-domains {
446 compatible = "rockchip,rv1108-pmu-io-voltage-domain";
452 compatible = "rockchip,rv1108-usbgrf", "syscon";
456 cru: clock-controller@20200000 {
457 compatible = "rockchip,rv1108-cru";
460 #clock-cells = <1>;
461 #reset-cells = <1>;
464 nfc: nand-controller@30100000 {
465 compatible = "rockchip,rv1108-nfc";
469 clock-names = "ahb", "nfc";
470 assigned-clocks = <&cru SCLK_NANDC>;
471 assigned-clock-rates = <150000000>;
476 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
481 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
482 fifo-depth = <0x100>;
483 max-frequency = <150000000>;
488 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
493 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
494 fifo-depth = <0x100>;
495 max-frequency = <150000000>;
500 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
505 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
506 fifo-depth = <0x100>;
507 max-frequency = <100000000>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
514 compatible = "generic-ehci";
519 phy-names = "usb";
524 compatible = "generic-ohci";
529 phy-names = "usb";
534 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
539 clock-names = "otg";
541 g-np-tx-fifo-size = <16>;
542 g-rx-fifo-size = <280>;
543 g-tx-fifo-size = <256 128 128 64 32 16>;
545 phy-names = "usb2-phy";
554 clock-names = "clk_sfc", "hclk_sfc";
555 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
556 pinctrl-names = "default";
561 compatible = "rockchip,rv1108-gmac";
565 interrupt-names = "macirq", "eth_wake_irq";
570 clock-names = "stmmaceth",
575 phy-mode = "rmii";
576 pinctrl-names = "default";
577 pinctrl-0 = <&rmii_pins>;
582 gic: interrupt-controller@32010000 {
583 compatible = "arm,gic-400";
584 interrupt-controller;
585 #interrupt-cells = <3>;
586 #address-cells = <0>;
596 compatible = "rockchip,rv1108-pinctrl";
599 #address-cells = <1>;
600 #size-cells = <1>;
604 compatible = "rockchip,gpio-bank";
609 gpio-controller;
610 #gpio-cells = <2>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
617 compatible = "rockchip,gpio-bank";
622 gpio-controller;
623 #gpio-cells = <2>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
630 compatible = "rockchip,gpio-bank";
635 gpio-controller;
636 #gpio-cells = <2>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
643 compatible = "rockchip,gpio-bank";
648 gpio-controller;
649 #gpio-cells = <2>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
655 pcfg_pull_up: pcfg-pull-up {
656 bias-pull-up;
659 pcfg_pull_down: pcfg-pull-down {
660 bias-pull-down;
663 pcfg_pull_none: pcfg-pull-none {
664 bias-disable;
667 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
668 drive-strength = <8>;
671 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
672 drive-strength = <12>;
675 pcfg_pull_none_smt: pcfg-pull-none-smt {
676 bias-disable;
677 input-schmitt-enable;
680 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
681 bias-pull-up;
682 drive-strength = <8>;
685 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
686 drive-strength = <4>;
689 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
690 bias-pull-up;
691 drive-strength = <4>;
694 pcfg_output_high: pcfg-output-high {
695 output-high;
698 pcfg_output_low: pcfg-output-low {
699 output-low;
702 pcfg_input_high: pcfg-input-high {
703 bias-pull-up;
704 input-enable;
708 emmc_bus8: emmc-bus8 {
719 emmc_clk: emmc-clk {
723 emmc_cmd: emmc-cmd {
729 sfc_bus4: sfc-bus4 {
737 sfc_bus2: sfc-bus2 {
743 sfc_cs0: sfc-cs0 {
748 sfc_clk: sfc-clk {
755 rmii_pins: rmii-pins {
770 i2c0_xfer: i2c0-xfer {
777 i2c1_xfer: i2c1-xfer {
784 i2c2m1_xfer: i2c2m1-xfer {
789 i2c2m1_pins: i2c2m1-pins {
796 i2c2m05v_xfer: i2c2m05v-xfer {
801 i2c2m05v_pins: i2c2m05v-pins {
808 i2c3_xfer: i2c3-xfer {
815 pwm0_pin: pwm0-pin {
821 pwm1_pin: pwm1-pin {
827 pwm2_pin: pwm2-pin {
833 pwm3_pin: pwm3-pin {
839 pwm4_pin: pwm4-pin {
845 pwm5_pin: pwm5-pin {
851 pwm6_pin: pwm6-pin {
857 pwm7_pin: pwm7-pin {
863 sdmmc_clk: sdmmc-clk {
867 sdmmc_cmd: sdmmc-cmd {
871 sdmmc_cd: sdmmc-cd {
875 sdmmc_bus1: sdmmc-bus1 {
879 sdmmc_bus4: sdmmc-bus4 {
888 spim0_clk: spim0-clk {
892 spim0_cs0: spim0-cs0 {
896 spim0_tx: spim0-tx {
900 spim0_rx: spim0-rx {
906 spim1_clk: spim1-clk {
910 spim1_cs0: spim1-cs0 {
914 spim1_rx: spim1-rx {
918 spim1_tx: spim1-tx {
924 otp_out: otp-out {
928 otp_pin: otp-pin {
934 uart0_xfer: uart0-xfer {
939 uart0_cts: uart0-cts {
943 uart0_rts: uart0-rts {
947 uart0_rts_pin: uart0-rts-pin {
953 uart1_xfer: uart1-xfer {
958 uart1_cts: uart1-cts {
962 uart1_rts: uart1-rts {
968 uart2m0_xfer: uart2m0-xfer {
975 uart2m1_xfer: uart2m1-xfer {
982 uart2_5v_cts: uart2_5v-cts {
986 uart2_5v_rts: uart2_5v-rts {