Lines Matching +full:rx +full:- +full:fifo +full:- +full:depth
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
35 #clock-cells = <0>;
36 clock-output-names = "xin24m";
40 compatible = "arm,mali-400";
43 clock-names = "bus", "core";
44 assigned-clocks = <&cru ACLK_GPU>;
45 assigned-clock-rates = <100000000>;
50 vpu: video-codec@10104000 {
51 compatible = "rockchip,rk3066-vpu";
55 interrupt-names = "vepu", "vdpu";
58 clock-names = "aclk_vdpu", "hclk_vdpu",
62 L2: cache-controller@10138000 {
63 compatible = "arm,pl310-cache";
65 cache-unified;
66 cache-level = <2>;
70 compatible = "arm,cortex-a9-scu";
74 global_timer: global-timer@1013c200 {
75 compatible = "arm,cortex-a9-global-timer";
81 local_timer: local-timer@1013c600 {
82 compatible = "arm,cortex-a9-twd-timer";
88 gic: interrupt-controller@1013d000 {
89 compatible = "arm,cortex-a9-gic";
90 interrupt-controller;
91 #interrupt-cells = <3>;
97 compatible = "snps,dw-apb-uart";
100 reg-shift = <2>;
101 reg-io-width = <1>;
102 clock-names = "baudclk", "apb_pclk";
108 compatible = "snps,dw-apb-uart";
111 reg-shift = <2>;
112 reg-io-width = <1>;
113 clock-names = "baudclk", "apb_pclk";
119 compatible = "rockchip,rk3066-qos", "syscon";
124 compatible = "rockchip,rk3066-qos", "syscon";
129 compatible = "rockchip,rk3066-qos", "syscon";
134 compatible = "rockchip,rk3066-qos", "syscon";
139 compatible = "rockchip,rk3066-qos", "syscon";
144 compatible = "rockchip,rk3066-qos", "syscon";
149 compatible = "rockchip,rk3066-qos", "syscon";
154 compatible = "rockchip,rk3066-qos", "syscon";
159 compatible = "rockchip,rk3066-usb", "snps,dwc2";
163 clock-names = "otg";
165 g-np-tx-fifo-size = <16>;
166 g-rx-fifo-size = <275>;
167 g-tx-fifo-size = <256 128 128 64 64 32>;
169 phy-names = "usb2-phy";
178 clock-names = "otg";
181 phy-names = "usb2-phy";
186 compatible = "snps,arc-emac";
189 #address-cells = <1>;
190 #size-cells = <0>;
195 clock-names = "hclk", "macref";
196 max-speed = <100>;
197 phy-mode = "rmii";
203 compatible = "rockchip,rk2928-dw-mshc";
207 clock-names = "biu", "ciu";
209 dma-names = "rx-tx";
210 fifo-depth = <256>;
212 reset-names = "reset";
217 compatible = "rockchip,rk2928-dw-mshc";
221 clock-names = "biu", "ciu";
223 dma-names = "rx-tx";
224 fifo-depth = <256>;
226 reset-names = "reset";
231 compatible = "rockchip,rk2928-dw-mshc";
235 clock-names = "biu", "ciu";
237 dma-names = "rx-tx";
238 fifo-depth = <256>;
240 reset-names = "reset";
244 nfc: nand-controller@10500000 {
245 compatible = "rockchip,rk2928-nfc";
249 clock-names = "ahb";
254 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
257 reboot-mode {
258 compatible = "syscon-reboot-mode";
260 mode-normal = <BOOT_NORMAL>;
261 mode-recovery = <BOOT_RECOVERY>;
262 mode-bootloader = <BOOT_FASTBOOT>;
263 mode-loader = <BOOT_BL_DOWNLOAD>;
268 compatible = "syscon", "simple-mfd";
272 dmac1_s: dma-controller@20018000 {
277 #dma-cells = <1>;
278 arm,pl330-broken-no-flushp;
279 arm,pl330-periph-burst;
281 clock-names = "apb_pclk";
284 dmac1_ns: dma-controller@2001c000 {
289 #dma-cells = <1>;
290 arm,pl330-broken-no-flushp;
291 arm,pl330-periph-burst;
293 clock-names = "apb_pclk";
298 compatible = "rockchip,rk3066-i2c";
301 #address-cells = <1>;
302 #size-cells = <0>;
306 clock-names = "i2c";
313 compatible = "rockchip,rk3066-i2c";
316 #address-cells = <1>;
317 #size-cells = <0>;
322 clock-names = "i2c";
328 compatible = "rockchip,rk2928-pwm";
330 #pwm-cells = <2>;
336 compatible = "rockchip,rk2928-pwm";
338 #pwm-cells = <2>;
344 compatible = "snps,dw-wdt";
352 compatible = "rockchip,rk2928-pwm";
354 #pwm-cells = <2>;
360 compatible = "rockchip,rk2928-pwm";
362 #pwm-cells = <2>;
368 compatible = "rockchip,rk3066-i2c";
371 #address-cells = <1>;
372 #size-cells = <0>;
377 clock-names = "i2c";
383 compatible = "rockchip,rk3066-i2c";
386 #address-cells = <1>;
387 #size-cells = <0>;
392 clock-names = "i2c";
398 compatible = "rockchip,rk3066-i2c";
401 #address-cells = <1>;
402 #size-cells = <0>;
407 clock-names = "i2c";
413 compatible = "snps,dw-apb-uart";
416 reg-shift = <2>;
417 reg-io-width = <1>;
418 clock-names = "baudclk", "apb_pclk";
424 compatible = "snps,dw-apb-uart";
427 reg-shift = <2>;
428 reg-io-width = <1>;
429 clock-names = "baudclk", "apb_pclk";
438 #io-channel-cells = <1>;
440 clock-names = "saradc", "apb_pclk";
442 reset-names = "saradc-apb";
447 compatible = "rockchip,rk3066-spi";
449 clock-names = "spiclk", "apb_pclk";
452 #address-cells = <1>;
453 #size-cells = <0>;
455 dma-names = "tx", "rx";
460 compatible = "rockchip,rk3066-spi";
462 clock-names = "spiclk", "apb_pclk";
465 #address-cells = <1>;
466 #size-cells = <0>;
468 dma-names = "tx", "rx";
472 dmac2: dma-controller@20078000 {
477 #dma-cells = <1>;
478 arm,pl330-broken-no-flushp;
479 arm,pl330-periph-burst;
481 clock-names = "apb_pclk";