Lines Matching +full:rx +full:- +full:sample +full:- +full:delay +full:- +full:ns
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a7";
33 operating-points-v2 = <&cpu0_opp_table>;
34 #cooling-cells = <2>; /* min followed by max */
35 clock-latency = <40000>;
37 enable-method = "psci";
42 compatible = "arm,cortex-a7";
45 operating-points-v2 = <&cpu0_opp_table>;
46 #cooling-cells = <2>; /* min followed by max */
47 enable-method = "psci";
52 compatible = "arm,cortex-a7";
55 operating-points-v2 = <&cpu0_opp_table>;
56 #cooling-cells = <2>; /* min followed by max */
57 enable-method = "psci";
62 compatible = "arm,cortex-a7";
65 operating-points-v2 = <&cpu0_opp_table>;
66 #cooling-cells = <2>; /* min followed by max */
67 enable-method = "psci";
72 compatible = "operating-points-v2";
73 opp-shared;
75 opp-408000000 {
76 opp-hz = /bits/ 64 <408000000>;
77 opp-microvolt = <950000>;
78 clock-latency-ns = <40000>;
79 opp-suspend;
81 opp-600000000 {
82 opp-hz = /bits/ 64 <600000000>;
83 opp-microvolt = <975000>;
85 opp-816000000 {
86 opp-hz = /bits/ 64 <816000000>;
87 opp-microvolt = <1000000>;
89 opp-1008000000 {
90 opp-hz = /bits/ 64 <1008000000>;
91 opp-microvolt = <1175000>;
93 opp-1200000000 {
94 opp-hz = /bits/ 64 <1200000000>;
95 opp-microvolt = <1275000>;
99 arm-pmu {
100 compatible = "arm,cortex-a7-pmu";
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
109 compatible = "arm,psci-1.0", "arm,psci-0.2";
114 compatible = "arm,armv7-timer";
115 arm,cpu-registers-not-fw-configured;
120 clock-frequency = <24000000>;
124 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "xin24m";
127 #clock-cells = <0>;
130 display_subsystem: display-subsystem {
131 compatible = "rockchip,display-subsystem";
136 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
139 clock-names = "i2s_clk", "i2s_hclk";
142 dma-names = "tx", "rx";
143 pinctrl-names = "default";
144 pinctrl-0 = <&i2s1_bus>;
149 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
152 clock-names = "i2s_clk", "i2s_hclk";
155 dma-names = "tx", "rx";
160 compatible = "rockchip,rk3228-spdif";
164 clock-names = "mclk", "hclk";
166 dma-names = "tx";
167 pinctrl-names = "default";
168 pinctrl-0 = <&spdif_tx>;
173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
176 clock-names = "i2s_clk", "i2s_hclk";
179 dma-names = "tx", "rx";
184 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
186 #address-cells = <1>;
187 #size-cells = <1>;
189 io_domains: io-domains {
190 compatible = "rockchip,rk3228-io-voltage-domain";
194 power: power-controller {
195 compatible = "rockchip,rk3228-power-controller";
196 #power-domain-cells = <1>;
197 #address-cells = <1>;
198 #size-cells = <0>;
200 power-domain@RK3228_PD_VIO {
213 #power-domain-cells = <0>;
216 power-domain@RK3228_PD_VOP {
222 #power-domain-cells = <0>;
225 power-domain@RK3228_PD_VPU {
230 #power-domain-cells = <0>;
233 power-domain@RK3228_PD_RKVDEC {
241 #power-domain-cells = <0>;
244 power-domain@RK3228_PD_GPU {
248 #power-domain-cells = <0>;
253 compatible = "rockchip,rk3228-usb2phy";
256 clock-names = "phyclk";
257 clock-output-names = "usb480m_phy0";
258 #clock-cells = <0>;
261 u2phy0_otg: otg-port {
265 interrupt-names = "otg-bvalid", "otg-id",
267 #phy-cells = <0>;
271 u2phy0_host: host-port {
273 interrupt-names = "linestate";
274 #phy-cells = <0>;
280 compatible = "rockchip,rk3228-usb2phy";
283 clock-names = "phyclk";
284 clock-output-names = "usb480m_phy1";
285 #clock-cells = <0>;
288 u2phy1_otg: otg-port {
290 interrupt-names = "linestate";
291 #phy-cells = <0>;
295 u2phy1_host: host-port {
297 interrupt-names = "linestate";
298 #phy-cells = <0>;
305 compatible = "snps,dw-apb-uart";
308 clock-frequency = <24000000>;
310 clock-names = "baudclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
313 reg-shift = <2>;
314 reg-io-width = <4>;
319 compatible = "snps,dw-apb-uart";
322 clock-frequency = <24000000>;
324 clock-names = "baudclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_xfer>;
327 reg-shift = <2>;
328 reg-io-width = <4>;
333 compatible = "snps,dw-apb-uart";
336 clock-frequency = <24000000>;
338 clock-names = "baudclk", "apb_pclk";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_xfer>;
341 reg-shift = <2>;
342 reg-io-width = <4>;
347 compatible = "rockchip,rk3228-efuse";
350 clock-names = "pclk_efuse";
351 #address-cells = <1>;
352 #size-cells = <1>;
364 compatible = "rockchip,rk3228-i2c";
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clock-names = "i2c";
371 pinctrl-names = "default";
372 pinctrl-0 = <&i2c0_xfer>;
377 compatible = "rockchip,rk3228-i2c";
380 #address-cells = <1>;
381 #size-cells = <0>;
382 clock-names = "i2c";
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c1_xfer>;
390 compatible = "rockchip,rk3228-i2c";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 clock-names = "i2c";
397 pinctrl-names = "default";
398 pinctrl-0 = <&i2c2_xfer>;
403 compatible = "rockchip,rk3228-i2c";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 clock-names = "i2c";
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c3_xfer>;
416 compatible = "rockchip,rk3228-spi";
419 #address-cells = <1>;
420 #size-cells = <0>;
422 clock-names = "spiclk", "apb_pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
429 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
437 compatible = "rockchip,rk3288-pwm";
439 #pwm-cells = <3>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pwm0_pin>;
447 compatible = "rockchip,rk3288-pwm";
449 #pwm-cells = <3>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pwm1_pin>;
457 compatible = "rockchip,rk3288-pwm";
459 #pwm-cells = <3>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pwm2_pin>;
467 compatible = "rockchip,rk3288-pwm";
469 #pwm-cells = <2>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm3_pin>;
477 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
481 clock-names = "timer", "pclk";
484 cru: clock-controller@110e0000 {
485 compatible = "rockchip,rk3228-cru";
488 #clock-cells = <1>;
489 #reset-cells = <1>;
490 assigned-clocks =
496 assigned-clock-rates =
509 #dma-cells = <1>;
510 arm,pl330-periph-burst;
512 clock-names = "apb_pclk";
515 thermal-zones {
516 cpu_thermal: cpu-thermal {
517 polling-delay-passive = <100>; /* milliseconds */
518 polling-delay = <5000>; /* milliseconds */
520 thermal-sensors = <&tsadc 0>;
540 cooling-maps {
543 cooling-device =
551 cooling-device =
562 compatible = "rockchip,rk3228-tsadc";
566 clock-names = "tsadc", "apb_pclk";
567 assigned-clocks = <&cru SCLK_TSADC>;
568 assigned-clock-rates = <32768>;
570 reset-names = "tsadc-apb";
571 pinctrl-names = "init", "default", "sleep";
572 pinctrl-0 = <&otp_pin>;
573 pinctrl-1 = <&otp_out>;
574 pinctrl-2 = <&otp_pin>;
575 #thermal-sensor-cells = <1>;
576 rockchip,hw-tshut-temp = <95000>;
580 hdmi_phy: hdmi-phy@12030000 {
581 compatible = "rockchip,rk3228-hdmi-phy";
584 clock-names = "sysclk", "refoclk", "refpclk";
585 #clock-cells = <0>;
586 clock-output-names = "hdmiphy_phy";
587 #phy-cells = <0>;
592 compatible = "rockchip,rk3228-mali", "arm,mali-400";
600 interrupt-names = "gp",
607 clock-names = "bus", "core";
608 power-domains = <&power RK3228_PD_GPU>;
613 vpu: video-codec@20020000 {
614 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
618 interrupt-names = "vepu", "vdpu";
620 clock-names = "aclk", "hclk";
622 power-domains = <&power RK3228_PD_VPU>;
630 clock-names = "aclk", "iface";
631 power-domains = <&power RK3228_PD_VPU>;
632 #iommu-cells = <0>;
635 vdec: video-codec@20030000 {
636 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
641 clock-names = "axi", "ahb", "cabac", "core";
642 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
643 assigned-clock-rates = <300000000>, <300000000>;
645 power-domains = <&power RK3228_PD_RKVDEC>;
653 clock-names = "aclk", "iface";
654 power-domains = <&power RK3228_PD_RKVDEC>;
655 #iommu-cells = <0>;
659 compatible = "rockchip,rk3228-vop";
663 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
665 reset-names = "axi", "ahb", "dclk";
667 power-domains = <&power RK3228_PD_VOP>;
671 #address-cells = <1>;
672 #size-cells = <0>;
676 remote-endpoint = <&hdmi_in_vop>;
686 clock-names = "aclk", "iface";
687 power-domains = <&power RK3228_PD_VOP>;
688 #iommu-cells = <0>;
693 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
697 clock-names = "aclk", "hclk", "sclk";
698 power-domains = <&power RK3228_PD_VIO>;
700 reset-names = "core", "axi", "ahb";
708 clock-names = "aclk", "iface";
709 power-domains = <&power RK3228_PD_VIO>;
710 #iommu-cells = <0>;
715 compatible = "rockchip,rk3228-dw-hdmi";
717 reg-io-width = <4>;
719 assigned-clocks = <&cru SCLK_HDMI_PHY>;
720 assigned-clock-parents = <&hdmi_phy>;
722 clock-names = "isfr", "iahb", "cec";
723 pinctrl-names = "default";
724 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
726 reset-names = "hdmi";
728 phy-names = "hdmi";
734 #address-cells = <1>;
735 #size-cells = <0>;
738 remote-endpoint = <&vop_out_hdmi>;
745 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
750 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
751 fifo-depth = <0x100>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
758 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
763 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
764 fifo-depth = <0x100>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
771 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
774 clock-frequency = <37500000>;
775 max-frequency = <37500000>;
778 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
779 bus-width = <8>;
780 rockchip,default-sample-phase = <158>;
781 fifo-depth = <0x100>;
782 pinctrl-names = "default";
783 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
785 reset-names = "reset";
790 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
795 clock-names = "otg";
797 g-np-tx-fifo-size = <16>;
798 g-rx-fifo-size = <280>;
799 g-tx-fifo-size = <256 128 128 64 32 16>;
801 phy-names = "usb2-phy";
806 compatible = "generic-ehci";
811 phy-names = "usb";
816 compatible = "generic-ohci";
821 phy-names = "usb";
826 compatible = "generic-ehci";
831 phy-names = "usb";
836 compatible = "generic-ohci";
841 phy-names = "usb";
846 compatible = "generic-ehci";
851 phy-names = "usb";
856 compatible = "generic-ohci";
861 phy-names = "usb";
866 compatible = "rockchip,rk3228-gmac";
869 interrupt-names = "macirq";
874 clock-names = "stmmaceth", "mac_clk_rx",
879 reset-names = "stmmaceth";
885 compatible = "rockchip,rk3228-qos", "syscon";
890 compatible = "rockchip,rk3228-qos", "syscon";
895 compatible = "rockchip,rk3228-qos", "syscon";
900 compatible = "rockchip,rk3228-qos", "syscon";
905 compatible = "rockchip,rk3228-qos", "syscon";
910 compatible = "rockchip,rk3228-qos", "syscon";
915 compatible = "rockchip,rk3228-qos", "syscon";
920 compatible = "rockchip,rk3228-qos", "syscon";
925 compatible = "rockchip,rk3228-qos", "syscon";
929 gic: interrupt-controller@32010000 {
930 compatible = "arm,gic-400";
931 interrupt-controller;
932 #interrupt-cells = <3>;
933 #address-cells = <0>;
943 compatible = "rockchip,rk3228-pinctrl";
945 #address-cells = <1>;
946 #size-cells = <1>;
950 compatible = "rockchip,gpio-bank";
955 gpio-controller;
956 #gpio-cells = <2>;
958 interrupt-controller;
959 #interrupt-cells = <2>;
963 compatible = "rockchip,gpio-bank";
968 gpio-controller;
969 #gpio-cells = <2>;
971 interrupt-controller;
972 #interrupt-cells = <2>;
976 compatible = "rockchip,gpio-bank";
981 gpio-controller;
982 #gpio-cells = <2>;
984 interrupt-controller;
985 #interrupt-cells = <2>;
989 compatible = "rockchip,gpio-bank";
994 gpio-controller;
995 #gpio-cells = <2>;
997 interrupt-controller;
998 #interrupt-cells = <2>;
1001 pcfg_pull_up: pcfg-pull-up {
1002 bias-pull-up;
1005 pcfg_pull_down: pcfg-pull-down {
1006 bias-pull-down;
1009 pcfg_pull_none: pcfg-pull-none {
1010 bias-disable;
1013 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1014 drive-strength = <12>;
1018 sdmmc_clk: sdmmc-clk {
1022 sdmmc_cmd: sdmmc-cmd {
1026 sdmmc_bus4: sdmmc-bus4 {
1035 sdio_clk: sdio-clk {
1039 sdio_cmd: sdio-cmd {
1043 sdio_bus4: sdio-bus4 {
1052 emmc_clk: emmc-clk {
1056 emmc_cmd: emmc-cmd {
1060 emmc_bus8: emmc-bus8 {
1073 rgmii_pins: rgmii-pins {
1091 rmii_pins: rmii-pins {
1104 phy_pins: phy-pins {
1111 hdmi_hpd: hdmi-hpd {
1115 hdmii2c_xfer: hdmii2c-xfer {
1120 hdmi_cec: hdmi-cec {
1126 i2c0_xfer: i2c0-xfer {
1133 i2c1_xfer: i2c1-xfer {
1140 i2c2_xfer: i2c2-xfer {
1147 i2c3_xfer: i2c3-xfer {
1154 spi0_clk: spi0-clk {
1157 spi0_cs0: spi0-cs0 {
1160 spi0_tx: spi0-tx {
1163 spi0_rx: spi0-rx {
1166 spi0_cs1: spi0-cs1 {
1172 spi1_clk: spi1-clk {
1175 spi1_cs0: spi1-cs0 {
1178 spi1_rx: spi1-rx {
1181 spi1_tx: spi1-tx {
1184 spi1_cs1: spi1-cs1 {
1190 i2s1_bus: i2s1-bus {
1204 pwm0_pin: pwm0-pin {
1210 pwm1_pin: pwm1-pin {
1216 pwm2_pin: pwm2-pin {
1222 pwm3_pin: pwm3-pin {
1228 spdif_tx: spdif-tx {
1234 otp_pin: otp-pin {
1238 otp_out: otp-out {
1244 uart0_xfer: uart0-xfer {
1249 uart0_cts: uart0-cts {
1253 uart0_rts: uart0-rts {
1259 uart1_xfer: uart1-xfer {
1264 uart1_cts: uart1-cts {
1268 uart1_rts: uart1-rts {
1274 uart2_xfer: uart2-xfer {
1279 uart21_xfer: uart21-xfer {
1284 uart2_cts: uart2-cts {
1288 uart2_rts: uart2-rts {