Lines Matching +full:rk3188 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
14 compatible = "rockchip,rk3188";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 clock-latency = <40000>;
28 operating-points-v2 = <&cpu0_opp_table>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
36 operating-points-v2 = <&cpu0_opp_table>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
44 operating-points-v2 = <&cpu0_opp_table>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
52 operating-points-v2 = <&cpu0_opp_table>;
58 compatible = "operating-points-v2";
59 opp-shared;
61 opp-312000000 {
62 opp-hz = /bits/ 64 <312000000>;
63 opp-microvolt = <875000>;
64 clock-latency-ns = <40000>;
66 opp-504000000 {
67 opp-hz = /bits/ 64 <504000000>;
68 opp-microvolt = <925000>;
70 opp-600000000 {
71 opp-hz = /bits/ 64 <600000000>;
72 opp-microvolt = <950000>;
73 opp-suspend;
75 opp-816000000 {
76 opp-hz = /bits/ 64 <816000000>;
77 opp-microvolt = <975000>;
79 opp-1008000000 {
80 opp-hz = /bits/ 64 <1008000000>;
81 opp-microvolt = <1075000>;
83 opp-1200000000 {
84 opp-hz = /bits/ 64 <1200000000>;
85 opp-microvolt = <1150000>;
87 opp-1416000000 {
88 opp-hz = /bits/ 64 <1416000000>;
89 opp-microvolt = <1250000>;
91 opp-1608000000 {
92 opp-hz = /bits/ 64 <1608000000>;
93 opp-microvolt = <1350000>;
97 display-subsystem {
98 compatible = "rockchip,display-subsystem";
103 compatible = "mmio-sram";
105 #address-cells = <1>;
106 #size-cells = <1>;
109 smp-sram@0 {
110 compatible = "rockchip,rk3066-smp-sram";
116 compatible = "rockchip,rk3188-vop";
120 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
121 power-domains = <&power RK3188_PD_VIO>;
123 reset-names = "axi", "ahb", "dclk";
127 #address-cells = <1>;
128 #size-cells = <0>;
133 compatible = "rockchip,rk3188-vop";
137 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
138 power-domains = <&power RK3188_PD_VIO>;
140 reset-names = "axi", "ahb", "dclk";
144 #address-cells = <1>;
145 #size-cells = <0>;
150 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
154 clock-names = "pclk", "timer";
158 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
162 clock-names = "pclk", "timer";
166 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2s0_bus>;
172 clock-names = "i2s_clk", "i2s_hclk";
174 dma-names = "tx", "rx";
175 rockchip,playback-channels = <2>;
176 rockchip,capture-channels = <2>;
177 #sound-dai-cells = <0>;
182 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
184 #sound-dai-cells = <0>;
186 clock-names = "mclk", "hclk";
188 dma-names = "tx";
190 pinctrl-names = "default";
191 pinctrl-0 = <&spdif_tx>;
195 cru: clock-controller@20000000 {
196 compatible = "rockchip,rk3188-cru";
200 #clock-cells = <1>;
201 #reset-cells = <1>;
205 compatible = "rockchip,rk3188-efuse";
207 #address-cells = <1>;
208 #size-cells = <1>;
210 clock-names = "pclk_efuse";
218 compatible = "rockchip,rk3188-pinctrl";
222 #address-cells = <1>;
223 #size-cells = <1>;
227 compatible = "rockchip,rk3188-gpio-bank0";
232 gpio-controller;
233 #gpio-cells = <2>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
240 compatible = "rockchip,gpio-bank";
245 gpio-controller;
246 #gpio-cells = <2>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
253 compatible = "rockchip,gpio-bank";
258 gpio-controller;
259 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
266 compatible = "rockchip,gpio-bank";
271 gpio-controller;
272 #gpio-cells = <2>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
278 pcfg_pull_up: pcfg-pull-up {
279 bias-pull-up;
282 pcfg_pull_down: pcfg-pull-down {
283 bias-pull-down;
286 pcfg_pull_none: pcfg-pull-none {
287 bias-disable;
291 emmc_clk: emmc-clk {
295 emmc_cmd: emmc-cmd {
299 emmc_rst: emmc-rst {
307 * flash/emmc is the boot-device.
312 emac_xfer: emac-xfer {
323 emac_mdio: emac-mdio {
330 i2c0_xfer: i2c0-xfer {
337 i2c1_xfer: i2c1-xfer {
344 i2c2_xfer: i2c2-xfer {
351 i2c3_xfer: i2c3-xfer {
358 i2c4_xfer: i2c4-xfer {
365 lcdc1_dclk: lcdc1-dclk {
369 lcdc1_den: lcdc1-den {
373 lcdc1_hsync: lcdc1-hsync {
377 lcdc1_vsync: lcdc1-vsync {
381 lcdc1_rgb24: ldcd1-rgb24 {
410 pwm0_out: pwm0-out {
416 pwm1_out: pwm1-out {
422 pwm2_out: pwm2-out {
428 pwm3_out: pwm3-out {
434 spi0_clk: spi0-clk {
437 spi0_cs0: spi0-cs0 {
440 spi0_tx: spi0-tx {
443 spi0_rx: spi0-rx {
446 spi0_cs1: spi0-cs1 {
452 spi1_clk: spi1-clk {
455 spi1_cs0: spi1-cs0 {
458 spi1_rx: spi1-rx {
461 spi1_tx: spi1-tx {
464 spi1_cs1: spi1-cs1 {
470 uart0_xfer: uart0-xfer {
475 uart0_cts: uart0-cts {
479 uart0_rts: uart0-rts {
485 uart1_xfer: uart1-xfer {
490 uart1_cts: uart1-cts {
494 uart1_rts: uart1-rts {
500 uart2_xfer: uart2-xfer {
508 uart3_xfer: uart3-xfer {
513 uart3_cts: uart3-cts {
517 uart3_rts: uart3-rts {
523 sd0_clk: sd0-clk {
527 sd0_cmd: sd0-cmd {
531 sd0_cd: sd0-cd {
535 sd0_wp: sd0-wp {
539 sd0_pwr: sd0-pwr {
543 sd0_bus1: sd0-bus-width1 {
547 sd0_bus4: sd0-bus-width4 {
556 sd1_clk: sd1-clk {
560 sd1_cmd: sd1-cmd {
564 sd1_cd: sd1-cd {
568 sd1_wp: sd1-wp {
572 sd1_bus1: sd1-bus-width1 {
576 sd1_bus4: sd1-bus-width4 {
585 i2s0_bus: i2s0-bus {
596 spdif_tx: spdif-tx {
604 compatible = "rockchip,rk3188-emac";
617 compatible = "rockchip,rk3188-mali", "arm,mali-400";
628 interrupt-names = "gp",
638 power-domains = <&power RK3188_PD_GPU>;
642 compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
644 io_domains: io-domains {
645 compatible = "rockchip,rk3188-io-voltage-domain";
650 compatible = "rockchip,rk3188-usb-phy",
651 "rockchip,rk3288-usb-phy";
652 #address-cells = <1>;
653 #size-cells = <0>;
656 usbphy0: usb-phy@10c {
659 clock-names = "phyclk";
660 #clock-cells = <0>;
661 #phy-cells = <0>;
664 usbphy1: usb-phy@11c {
667 clock-names = "phyclk";
668 #clock-cells = <0>;
669 #phy-cells = <0>;
675 compatible = "rockchip,rk3188-i2c";
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c0_xfer>;
681 compatible = "rockchip,rk3188-i2c";
682 pinctrl-names = "default";
683 pinctrl-0 = <&i2c1_xfer>;
687 compatible = "rockchip,rk3188-i2c";
688 pinctrl-names = "default";
689 pinctrl-0 = <&i2c2_xfer>;
693 compatible = "rockchip,rk3188-i2c";
694 pinctrl-names = "default";
695 pinctrl-0 = <&i2c3_xfer>;
699 compatible = "rockchip,rk3188-i2c";
700 pinctrl-names = "default";
701 pinctrl-0 = <&i2c4_xfer>;
705 power: power-controller {
706 compatible = "rockchip,rk3188-power-controller";
707 #power-domain-cells = <1>;
708 #address-cells = <1>;
709 #size-cells = <0>;
711 power-domain@RK3188_PD_VIO {
731 #power-domain-cells = <0>;
734 power-domain@RK3188_PD_VIDEO {
741 #power-domain-cells = <0>;
744 power-domain@RK3188_PD_GPU {
748 #power-domain-cells = <0>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&pwm0_out>;
759 pinctrl-names = "default";
760 pinctrl-0 = <&pwm1_out>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pwm2_out>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&pwm3_out>;
774 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
775 pinctrl-names = "default";
776 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
780 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
781 pinctrl-names = "default";
782 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
786 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
787 pinctrl-names = "default";
788 pinctrl-0 = <&uart0_xfer>;
792 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
793 pinctrl-names = "default";
794 pinctrl-0 = <&uart1_xfer>;
798 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
799 pinctrl-names = "default";
800 pinctrl-0 = <&uart2_xfer>;
804 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
805 pinctrl-names = "default";
806 pinctrl-0 = <&uart3_xfer>;
810 compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
811 power-domains = <&power RK3188_PD_VIDEO>;
815 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";