Lines Matching refs:gcc
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
186 gcc: clock-controller@1800000 { label
187 compatible = "qcom,gcc-ipq4019";
196 clocks = <&gcc GCC_PRNG_AHB_CLK>;
228 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
229 <&gcc GCC_DCD_XO_CLK>;
238 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
249 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
250 <&gcc GCC_BLSP1_AHB_CLK>;
263 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
264 <&gcc GCC_BLSP1_AHB_CLK>;
277 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
278 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
291 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
292 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
305 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
316 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
317 <&gcc GCC_CRYPTO_AXI_CLK>,
318 <&gcc GCC_CRYPTO_CLK>;
380 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
381 <&gcc GCC_BLSP1_AHB_CLK>;
392 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
393 <&gcc GCC_BLSP1_AHB_CLK>;
437 clocks = <&gcc GCC_PCIE_AHB_CLK>,
438 <&gcc GCC_PCIE_AXI_M_CLK>,
439 <&gcc GCC_PCIE_AXI_S_CLK>;
444 resets = <&gcc PCIE_AXI_M_ARES>,
445 <&gcc PCIE_AXI_S_ARES>,
446 <&gcc PCIE_PIPE_ARES>,
447 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
448 <&gcc PCIE_AXI_S_XPU_ARES>,
449 <&gcc PCIE_PARF_XPU_ARES>,
450 <&gcc PCIE_PHY_ARES>,
451 <&gcc PCIE_AXI_M_STICKY_ARES>,
452 <&gcc PCIE_PIPE_STICKY_ARES>,
453 <&gcc PCIE_PWR_ARES>,
454 <&gcc PCIE_AHB_ARES>,
455 <&gcc PCIE_PHY_AHB_ARES>;
476 clocks = <&gcc GCC_QPIC_CLK>;
488 clocks = <&gcc GCC_QPIC_CLK>,
489 <&gcc GCC_QPIC_AHB_CLK>;
510 resets = <&gcc WIFI0_CPU_INIT_RESET>,
511 <&gcc WIFI0_RADIO_SRIF_RESET>,
512 <&gcc WIFI0_RADIO_WARM_RESET>,
513 <&gcc WIFI0_RADIO_COLD_RESET>,
514 <&gcc WIFI0_CORE_WARM_RESET>,
515 <&gcc WIFI0_CORE_COLD_RESET>;
519 clocks = <&gcc GCC_WCSS2G_CLK>,
520 <&gcc GCC_WCSS2G_REF_CLK>,
521 <&gcc GCC_WCSS2G_RTC_CLK>;
552 resets = <&gcc WIFI1_CPU_INIT_RESET>,
553 <&gcc WIFI1_RADIO_SRIF_RESET>,
554 <&gcc WIFI1_RADIO_WARM_RESET>,
555 <&gcc WIFI1_RADIO_COLD_RESET>,
556 <&gcc WIFI1_CORE_WARM_RESET>,
557 <&gcc WIFI1_CORE_COLD_RESET>;
561 clocks = <&gcc GCC_WCSS5G_CLK>,
562 <&gcc GCC_WCSS5G_REF_CLK>,
563 <&gcc GCC_WCSS5G_RTC_CLK>;
624 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
634 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
644 clocks = <&gcc GCC_USB3_MASTER_CLK>,
645 <&gcc GCC_USB3_SLEEP_CLK>,
646 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
666 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
676 clocks = <&gcc GCC_USB2_MASTER_CLK>,
677 <&gcc GCC_USB2_SLEEP_CLK>,
678 <&gcc GCC_USB2_MOCK_UTMI_CLK>;