Lines Matching +full:lpc +full:- +full:io +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
19 clock-output-names = "refclk";
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <800000000>;
27 clock-output-names = "sysbypck";
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <800000000>;
35 clock-output-names = "mcbypck";
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <125000000>;
43 clock-output-names = "clk_rg1refck";
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <125000000>;
51 clock-output-names = "clk_rg2refck";
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <50000000>;
58 clock-output-names = "clk_xin";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&gic>;
69 compatible = "arm,cortex-a9-scu";
70 reg = <0x3fe000 0x1000>;
73 l2: cache-controller@3fc000 {
74 compatible = "arm,pl310-cache";
75 reg = <0x3fc000 0x1000>;
77 cache-unified;
78 cache-level = <2>;
80 arm,shared-override;
83 gic: interrupt-controller@3ff000 {
84 compatible = "arm,cortex-a9-gic";
85 interrupt-controller;
86 #interrupt-cells = <3>;
87 reg = <0x3ff000 0x1000>,
92 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
93 reg = <0x800000 0x1000>;
97 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
98 reg = <0x801000 0x6C>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "simple-bus";
106 interrupt-parent = <&gic>;
110 compatible = "nuvoton,npcm750-reset";
111 reg = <0xf0801000 0x70>;
112 #reset-cells = <2>;
115 clk: clock-controller@f0801000 {
116 compatible = "nuvoton,npcm750-clk", "syscon";
117 #clock-cells = <1>;
118 clock-controller;
119 reg = <0xf0801000 0x1000>;
120 clock-names = "refclk", "sysbypck", "mcbypck";
127 reg = <0xf0802000 0x2000>;
129 interrupt-names = "macirq";
132 clock-names = "stmmaceth", "clk_gmac";
133 pinctrl-names = "default";
134 pinctrl-0 = <&rg1_pins
140 compatible = "nuvoton,npcm750-ehci";
141 reg = <0xf0806000 0x1000>;
147 compatible = "nuvoton,npcm750-fiu";
148 #address-cells = <1>;
149 #size-cells = <0>;
150 reg = <0xfb000000 0x1000>;
151 reg-names = "control", "memory";
153 clock-names = "clk_spi0";
158 compatible = "nuvoton,npcm750-fiu";
159 #address-cells = <1>;
160 #size-cells = <0>;
161 reg = <0xc0000000 0x1000>;
162 reg-names = "control", "memory";
164 clock-names = "clk_spi3";
165 pinctrl-names = "default";
166 pinctrl-0 = <&spi3_pins>;
171 compatible = "nuvoton,npcm750-fiu";
172 #address-cells = <1>;
173 #size-cells = <0>;
174 reg = <0xfb001000 0x1000>;
175 reg-names = "control", "memory";
177 clock-names = "clk_spix";
182 #address-cells = <1>;
183 #size-cells = <1>;
184 compatible = "simple-bus";
185 interrupt-parent = <&gic>;
189 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
190 reg = <0x7000 0x40>;
191 reg-io-width = <1>;
193 #address-cells = <1>;
194 #size-cells = <1>;
198 compatible = "nuvoton,npcm750-kcs-bmc";
199 reg = <0x0 0x40>;
206 compatible = "nuvoton,npcm750-kcs-bmc";
207 reg = <0x0 0x40>;
214 compatible = "nuvoton,npcm750-kcs-bmc";
215 reg = <0x0 0x40>;
223 compatible = "nuvoton,npcm750-pspi";
224 reg = <0x200000 0x1000>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pspi1_pins>;
227 #address-cells = <1>;
228 #size-cells = <0>;
231 clock-names = "clk_apb5";
237 compatible = "nuvoton,npcm750-pspi";
238 reg = <0x201000 0x1000>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pspi2_pins>;
241 #address-cells = <1>;
242 #size-cells = <0>;
245 clock-names = "clk_apb5";
251 compatible = "nuvoton,npcm750-timer";
253 reg = <0x8000 0x1C>;
258 compatible = "nuvoton,npcm750-wdt";
260 reg = <0x801C 0x4>;
266 compatible = "nuvoton,npcm750-wdt";
268 reg = <0x901C 0x4>;
274 compatible = "nuvoton,npcm750-wdt";
276 reg = <0xa01C 0x4>;
282 compatible = "nuvoton,npcm750-uart";
283 reg = <0x1000 0x1000>;
286 reg-shift = <2>;
291 compatible = "nuvoton,npcm750-uart";
292 reg = <0x2000 0x1000>;
295 reg-shift = <2>;
300 compatible = "nuvoton,npcm750-uart";
301 reg = <0x3000 0x1000>;
304 reg-shift = <2>;
309 compatible = "nuvoton,npcm750-uart";
310 reg = <0x4000 0x1000>;
313 reg-shift = <2>;
318 compatible = "nuvoton,npcm750-rng";
319 reg = <0xb000 0x8>;
324 compatible = "nuvoton,npcm750-adc";
325 reg = <0xc000 0x8>;
332 pwm_fan: pwm-fan-controller@103000 {
333 #address-cells = <1>;
334 #size-cells = <0>;
335 compatible = "nuvoton,npcm750-pwm-fan";
336 reg = <0x103000 0x2000>, <0x180000 0x8000>;
337 reg-names = "pwm", "fan";
340 clock-names = "pwm","fan";
349 pinctrl-names = "default";
350 pinctrl-0 = <&pwm0_pins &pwm1_pins
366 reg = <0x80000 0x1000>;
367 compatible = "nuvoton,npcm750-i2c";
368 #address-cells = <1>;
369 #size-cells = <0>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&smb0_pins>;
378 reg = <0x81000 0x1000>;
379 compatible = "nuvoton,npcm750-i2c";
380 #address-cells = <1>;
381 #size-cells = <0>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&smb1_pins>;
390 reg = <0x82000 0x1000>;
391 compatible = "nuvoton,npcm750-i2c";
392 #address-cells = <1>;
393 #size-cells = <0>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&smb2_pins>;
402 reg = <0x83000 0x1000>;
403 compatible = "nuvoton,npcm750-i2c";
404 #address-cells = <1>;
405 #size-cells = <0>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&smb3_pins>;
414 reg = <0x84000 0x1000>;
415 compatible = "nuvoton,npcm750-i2c";
416 #address-cells = <1>;
417 #size-cells = <0>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&smb4_pins>;
426 reg = <0x85000 0x1000>;
427 compatible = "nuvoton,npcm750-i2c";
428 #address-cells = <1>;
429 #size-cells = <0>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&smb5_pins>;
438 reg = <0x86000 0x1000>;
439 compatible = "nuvoton,npcm750-i2c";
440 #address-cells = <1>;
441 #size-cells = <0>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&smb6_pins>;
450 reg = <0x87000 0x1000>;
451 compatible = "nuvoton,npcm750-i2c";
452 #address-cells = <1>;
453 #size-cells = <0>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&smb7_pins>;
462 reg = <0x88000 0x1000>;
463 compatible = "nuvoton,npcm750-i2c";
464 #address-cells = <1>;
465 #size-cells = <0>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&smb8_pins>;
474 reg = <0x89000 0x1000>;
475 compatible = "nuvoton,npcm750-i2c";
476 #address-cells = <1>;
477 #size-cells = <0>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&smb9_pins>;
486 reg = <0x8a000 0x1000>;
487 compatible = "nuvoton,npcm750-i2c";
488 #address-cells = <1>;
489 #size-cells = <0>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&smb10_pins>;
498 reg = <0x8b000 0x1000>;
499 compatible = "nuvoton,npcm750-i2c";
500 #address-cells = <1>;
501 #size-cells = <0>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&smb11_pins>;
510 reg = <0x8c000 0x1000>;
511 compatible = "nuvoton,npcm750-i2c";
512 #address-cells = <1>;
513 #size-cells = <0>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&smb12_pins>;
522 reg = <0x8d000 0x1000>;
523 compatible = "nuvoton,npcm750-i2c";
524 #address-cells = <1>;
525 #size-cells = <0>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&smb13_pins>;
534 reg = <0x8e000 0x1000>;
535 compatible = "nuvoton,npcm750-i2c";
536 #address-cells = <1>;
537 #size-cells = <0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&smb14_pins>;
546 reg = <0x8f000 0x1000>;
547 compatible = "nuvoton,npcm750-i2c";
548 #address-cells = <1>;
549 #size-cells = <0>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&smb15_pins>;
560 #address-cells = <1>;
561 #size-cells = <1>;
562 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
565 gpio-controller;
566 #gpio-cells = <2>;
567 reg = <0x0 0x80>;
569 gpio-ranges = <&pinctrl 0 0 32>;
572 gpio-controller;
573 #gpio-cells = <2>;
574 reg = <0x1000 0x80>;
576 gpio-ranges = <&pinctrl 0 32 32>;
579 gpio-controller;
580 #gpio-cells = <2>;
581 reg = <0x2000 0x80>;
583 gpio-ranges = <&pinctrl 0 64 32>;
586 gpio-controller;
587 #gpio-cells = <2>;
588 reg = <0x3000 0x80>;
590 gpio-ranges = <&pinctrl 0 96 32>;
593 gpio-controller;
594 #gpio-cells = <2>;
595 reg = <0x4000 0x80>;
597 gpio-ranges = <&pinctrl 0 128 32>;
600 gpio-controller;
601 #gpio-cells = <2>;
602 reg = <0x5000 0x80>;
604 gpio-ranges = <&pinctrl 0 160 32>;
607 gpio-controller;
608 #gpio-cells = <2>;
609 reg = <0x6000 0x80>;
611 gpio-ranges = <&pinctrl 0 192 32>;
614 gpio-controller;
615 #gpio-cells = <2>;
616 reg = <0x7000 0x80>;
618 gpio-ranges = <&pinctrl 0 224 32>;
621 iox1_pins: iox1-pins {
625 iox2_pins: iox2-pins {
629 smb1d_pins: smb1d-pins {
633 smb2d_pins: smb2d-pins {
637 lkgpo1_pins: lkgpo1-pins {
641 lkgpo2_pins: lkgpo2-pins {
645 ioxh_pins: ioxh-pins {
649 gspi_pins: gspi-pins {
653 smb5b_pins: smb5b-pins {
657 smb5c_pins: smb5c-pins {
661 lkgpo0_pins: lkgpo0-pins {
665 pspi2_pins: pspi2-pins {
669 smb4den_pins: smb4den-pins {
673 smb4b_pins: smb4b-pins {
677 smb4c_pins: smb4c-pins {
681 smb15_pins: smb15-pins {
685 smb4d_pins: smb4d-pins {
689 smb14_pins: smb14-pins {
693 smb5_pins: smb5-pins {
697 smb4_pins: smb4-pins {
701 smb3_pins: smb3-pins {
705 spi0cs1_pins: spi0cs1-pins {
709 spi0cs2_pins: spi0cs2-pins {
713 spi0cs3_pins: spi0cs3-pins {
717 smb3c_pins: smb3c-pins {
721 smb3b_pins: smb3b-pins {
725 bmcuart0a_pins: bmcuart0a-pins {
729 uart1_pins: uart1-pins {
733 jtag2_pins: jtag2-pins {
737 bmcuart1_pins: bmcuart1-pins {
741 uart2_pins: uart2-pins {
745 bmcuart0b_pins: bmcuart0b-pins {
749 r1err_pins: r1err-pins {
753 r1md_pins: r1md-pins {
757 smb3d_pins: smb3d-pins {
761 fanin0_pins: fanin0-pins {
765 fanin1_pins: fanin1-pins {
769 fanin2_pins: fanin2-pins {
773 fanin3_pins: fanin3-pins {
777 fanin4_pins: fanin4-pins {
781 fanin5_pins: fanin5-pins {
785 fanin6_pins: fanin6-pins {
789 fanin7_pins: fanin7-pins {
793 fanin8_pins: fanin8-pins {
797 fanin9_pins: fanin9-pins {
801 fanin10_pins: fanin10-pins {
805 fanin11_pins: fanin11-pins {
809 fanin12_pins: fanin12-pins {
813 fanin13_pins: fanin13-pins {
817 fanin14_pins: fanin14-pins {
821 fanin15_pins: fanin15-pins {
825 pwm0_pins: pwm0-pins {
829 pwm1_pins: pwm1-pins {
833 pwm2_pins: pwm2-pins {
837 pwm3_pins: pwm3-pins {
841 r2_pins: r2-pins {
845 r2err_pins: r2err-pins {
849 r2md_pins: r2md-pins {
853 ga20kbc_pins: ga20kbc-pins {
857 smb5d_pins: smb5d-pins {
861 lpc_pins: lpc-pins {
862 groups = "lpc";
863 function = "lpc";
865 espi_pins: espi-pins {
869 rg1_pins: rg1-pins {
873 rg1mdio_pins: rg1mdio-pins {
877 rg2_pins: rg2-pins {
881 ddr_pins: ddr-pins {
885 smb0_pins: smb0-pins {
889 smb1_pins: smb1-pins {
893 smb2_pins: smb2-pins {
897 smb2c_pins: smb2c-pins {
901 smb2b_pins: smb2b-pins {
905 smb1c_pins: smb1c-pins {
909 smb1b_pins: smb1b-pins {
913 smb8_pins: smb8-pins {
917 smb9_pins: smb9-pins {
921 smb10_pins: smb10-pins {
925 smb11_pins: smb11-pins {
929 sd1_pins: sd1-pins {
933 sd1pwr_pins: sd1pwr-pins {
937 pwm4_pins: pwm4-pins {
941 pwm5_pins: pwm5-pins {
945 pwm6_pins: pwm6-pins {
949 pwm7_pins: pwm7-pins {
953 mmc8_pins: mmc8-pins {
957 mmc_pins: mmc-pins {
961 mmcwp_pins: mmcwp-pins {
965 mmccd_pins: mmccd-pins {
969 mmcrst_pins: mmcrst-pins {
973 clkout_pins: clkout-pins {
977 serirq_pins: serirq-pins {
981 lpcclk_pins: lpcclk-pins {
985 scipme_pins: scipme-pins {
989 sci_pins: sci-pins {
993 smb6_pins: smb6-pins {
997 smb7_pins: smb7-pins {
1001 pspi1_pins: pspi1-pins {
1005 faninx_pins: faninx-pins {
1009 r1_pins: r1-pins {
1013 spi3_pins: spi3-pins {
1017 spi3cs1_pins: spi3cs1-pins {
1021 spi3quad_pins: spi3quad-pins {
1025 spi3cs2_pins: spi3cs2-pins {
1029 spi3cs3_pins: spi3cs3-pins {
1033 nprd_smi_pins: nprd-smi-pins {
1037 smb0b_pins: smb0b-pins {
1041 smb0c_pins: smb0c-pins {
1045 smb0den_pins: smb0den-pins {
1049 smb0d_pins: smb0d-pins {
1053 ddc_pins: ddc-pins {
1057 rg2mdio_pins: rg2mdio-pins {
1061 wdog1_pins: wdog1-pins {
1065 wdog2_pins: wdog2-pins {
1069 smb12_pins: smb12-pins {
1073 smb13_pins: smb13-pins {
1077 spix_pins: spix-pins {
1081 spixcs1_pins: spixcs1-pins {
1085 clkreq_pins: clkreq-pins {
1089 hgpio0_pins: hgpio0-pins {
1093 hgpio1_pins: hgpio1-pins {
1097 hgpio2_pins: hgpio2-pins {
1101 hgpio3_pins: hgpio3-pins {
1105 hgpio4_pins: hgpio4-pins {
1109 hgpio5_pins: hgpio5-pins {
1113 hgpio6_pins: hgpio6-pins {
1117 hgpio7_pins: hgpio7-pins {