Lines Matching +full:0 +full:x10008000
73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
159 thermal-sensors = <&thermal 0>;
230 reg = <0 0x10000000 0 0x1000>;
238 reg = <0 0x10001000 0 0x1000>;
247 reg = <0 0x10003000 0 0x1000>;
254 reg = <0 0x1000b000 0 0x1000>;
268 reg = <0 0x10005000 0 0x1000>;
276 reg = <0 0x10006000 0 0x1000>;
287 reg = <0 0x10007000 0 0x100>;
293 reg = <0 0x10008000 0 0x80>;
302 reg = <0 0x1000d000 0 0x1000>;
314 reg = <0 0x10013000 0 0x1000>;
327 reg = <0 0x10200100 0 0x1c>;
333 reg = <0 0x10206000 0 0x1000>;
337 reg = <0x424 0xc>;
345 reg = <0 0x10209000 0 0x1000>;
351 reg = <0 0x1020f000 0 0x1000>;
361 reg = <0 0x10211000 0 0x1000>,
362 <0 0x10212000 0 0x2000>,
363 <0 0x10214000 0 0x2000>,
364 <0 0x10216000 0 0x2000>;
370 reg = <0 0x11001000 0 0x1000>;
379 reg = <0 0x11002000 0 0x400>;
390 reg = <0 0x11003000 0 0x400>;
401 reg = <0 0x11004000 0 0x400>;
412 reg = <0 0x11005000 0 0x400>;
422 reg = <0 0x11006000 0 0x1000>;
439 reg = <0 0x11007000 0 0x70>,
440 <0 0x11000200 0 0x80>;
447 #size-cells = <0>;
454 reg = <0 0x11008000 0 0x70>,
455 <0 0x11000280 0 0x80>;
462 #size-cells = <0>;
469 reg = <0 0x11009000 0 0x70>,
470 <0 0x11000300 0 0x80>;
477 #size-cells = <0>;
485 #size-cells = <0>;
486 reg = <0 0x1100a000 0 0x100>;
499 reg = <0 0x1100b000 0 0x1000>;
500 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
514 reg = <0 0x1100c000 0 0x1000>;
526 reg = <0 0x1100d000 0 0x1000>;
535 #size-cells = <0>;
541 reg = <0 0x1100e000 0 0x1000>;
551 reg = <0 0x11014000 0 0x1000>;
556 #size-cells = <0>;
564 #size-cells = <0>;
565 reg = <0 0x11016000 0 0x100>;
578 #size-cells = <0>;
579 reg = <0 0x11017000 0 0x1000>;
592 reg = <0 0x11220000 0 0x2000>;
679 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
686 reg = <0 0x11230000 0 0x1000>;
697 reg = <0 0x11240000 0 0x1000>;
709 reg = <0 0x16000000 0 0x1000>;
717 reg = <0 0x1a000000 0 0x1000>;
725 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
726 <0 0x1a142000 0 0x1000>, /* Port0 registers */
727 <0 0x1a143000 0 0x1000>, /* Port1 registers */
728 <0 0x1a144000 0 0x1000>; /* Port2 registers */
733 interrupt-map-mask = <0xf800 0 0 0>;
734 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
735 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
736 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
751 bus-range = <0x00 0xff>;
753 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
754 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
756 pcie@0,0 {
757 reg = <0x0000 0 0 0 0>;
761 interrupt-map-mask = <0 0 0 0>;
762 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
767 pcie@1,0 {
768 reg = <0x0800 0 0 0 0>;
772 interrupt-map-mask = <0 0 0 0>;
773 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
778 pcie@2,0 {
779 reg = <0x1000 0 0 0 0>;
783 interrupt-map-mask = <0 0 0 0>;
784 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
793 reg = <0 0x1a149000 0 0x0700>;
800 reg = <0 0x1a149900 0 0x0700>;
811 reg = <0 0x1a14a000 0 0x0700>;
818 reg = <0 0x1a14a900 0 0x0700>;
829 reg = <0 0x1a1c0000 0 0x1000>,
830 <0 0x1a1c4700 0 0x0100>;
844 reg = <0 0x1a1c4000 0 0x0700>;
851 reg = <0 0x1a1c4800 0 0x0100>;
859 reg = <0 0x1a1c4900 0 0x0700>;
870 reg = <0 0x1a240000 0 0x1000>,
871 <0 0x1a244700 0 0x0100>;
885 reg = <0 0x1a244000 0 0x0700>;
892 reg = <0 0x1a244800 0 0x0100>;
900 reg = <0 0x1a244900 0 0x0700>;
912 reg = <0 0x1b000000 0 0x1000>;
919 reg = <0 0x1b007000 0 0x1000>;
931 reg = <0 0x1b100000 0 0x20000>;
949 #size-cells = <0>;
955 reg = <0 0x1b240000 0 0x20000>;
971 reg = <0 0x1c000000 0 0x1000>;