Lines Matching +full:mux +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
31 L2: l2-cache {
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0x3>;
37 compatible = "mrvl,axi-bus", "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
50 clock-names = "core", "bus";
51 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
54 intc: interrupt-controller@d4282000 {
55 compatible = "mrvl,mmp2-intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
59 mrvl,intc-nr-irqs = <64>;
62 intcmux4: interrupt-controller@d4282150 {
63 compatible = "mrvl,mmp2-mux-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
68 reg-names = "mux status", "mux mask";
69 mrvl,intc-nr-irqs = <2>;
72 intcmux5: interrupt-controller@d4282154 {
73 compatible = "mrvl,mmp2-mux-intc";
75 interrupt-controller;
76 #interrupt-cells = <1>;
78 reg-names = "mux status", "mux mask";
79 mrvl,intc-nr-irqs = <2>;
80 mrvl,clr-mfp-irq = <1>;
83 intcmux9: interrupt-controller@d4282180 {
84 compatible = "mrvl,mmp2-mux-intc";
86 interrupt-controller;
87 #interrupt-cells = <1>;
89 reg-names = "mux status", "mux mask";
90 mrvl,intc-nr-irqs = <3>;
93 intcmux17: interrupt-controller@d4282158 {
94 compatible = "mrvl,mmp2-mux-intc";
96 interrupt-controller;
97 #interrupt-cells = <1>;
99 reg-names = "mux status", "mux mask";
100 mrvl,intc-nr-irqs = <5>;
103 intcmux35: interrupt-controller@d428215c {
104 compatible = "mrvl,mmp2-mux-intc";
106 interrupt-controller;
107 #interrupt-cells = <1>;
109 reg-names = "mux status", "mux mask";
110 mrvl,intc-nr-irqs = <15>;
113 intcmux51: interrupt-controller@d4282160 {
114 compatible = "mrvl,mmp2-mux-intc";
116 interrupt-controller;
117 #interrupt-cells = <1>;
119 reg-names = "mux status", "mux mask";
120 mrvl,intc-nr-irqs = <2>;
123 intcmux55: interrupt-controller@d4282188 {
124 compatible = "mrvl,mmp2-mux-intc";
126 interrupt-controller;
127 #interrupt-cells = <1>;
129 reg-names = "mux status", "mux mask";
130 mrvl,intc-nr-irqs = <2>;
133 usb_phy0: usb-phy@d4207000 {
134 compatible = "marvell,mmp2-usb-phy";
136 #phy-cells = <0>;
140 usb_otg0: usb-otg@d4208000 {
141 compatible = "marvell,pxau2o-ehci";
145 clock-names = "USBCLK";
147 phy-names = "usb";
152 compatible = "mrvl,pxav3-mmc";
155 clock-names = "io";
161 compatible = "mrvl,pxav3-mmc";
164 clock-names = "io";
170 compatible = "mrvl,pxav3-mmc";
173 clock-names = "io";
179 compatible = "mrvl,pxav3-mmc";
182 clock-names = "io";
188 compatible = "marvell,mmp2-ccic";
192 clock-names = "axi";
193 #clock-cells = <0>;
194 clock-output-names = "mclk";
199 compatible = "marvell,mmp2-ccic";
203 clock-names = "axi";
204 #clock-cells = <0>;
205 clock-output-names = "mclk";
209 adma0: dma-controller@d42a0800 {
210 compatible = "marvell,adma-1.0";
213 #dma-cells = <1>;
219 adma1: dma-controller@d42a0900 {
220 compatible = "marvell,adma-1.0";
223 #dma-cells = <1>;
228 compatible = "marvell,mmp2-audio-clock";
230 clock-names = "audio", "vctcxo", "i2s0", "i2s1";
235 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
236 #clock-cells = <1>;
240 sspa0: audio-controller@d42a0c00 {
241 compatible = "marvell,mmp-sspa";
245 clock-names = "audio", "bitclk";
248 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
249 #sound-dai-cells = <0>;
253 sspa1: audio-controller@d42a0d00 {
254 compatible = "marvell,mmp-sspa";
258 clock-names = "audio", "bitclk";
261 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
262 #sound-dai-cells = <0>;
268 compatible = "mrvl,apb-bus", "simple-bus";
269 #address-cells = <1>;
270 #size-cells = <1>;
274 dma-controller@d4000000 {
275 compatible = "marvell,pdma-1.0";
278 #dma-channels = <16>;
283 compatible = "mrvl,mmp-timer";
290 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
295 reg-shift = <2>;
300 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
305 reg-shift = <2>;
310 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
315 reg-shift = <2>;
320 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
325 reg-shift = <2>;
330 compatible = "marvell,mmp2-gpio";
331 #address-cells = <1>;
332 #size-cells = <1>;
334 gpio-controller;
335 #gpio-cells = <2>;
337 interrupt-names = "gpio_mux";
340 interrupt-controller;
341 #interrupt-cells = <2>;
370 compatible = "mrvl,mmp-twsi";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 mrvl,i2c-fast-mode;
382 compatible = "mrvl,mmp-twsi";
384 interrupt-parent = <&intcmux17>;
388 #address-cells = <1>;
389 #size-cells = <0>;
394 compatible = "mrvl,mmp-twsi";
396 interrupt-parent = <&intcmux17>;
400 #address-cells = <1>;
401 #size-cells = <0>;
406 compatible = "mrvl,mmp-twsi";
408 interrupt-parent = <&intcmux17>;
412 #address-cells = <1>;
413 #size-cells = <0>;
419 compatible = "mrvl,mmp-twsi";
421 interrupt-parent = <&intcmux17>;
425 #address-cells = <1>;
426 #size-cells = <0>;
431 compatible = "mrvl,mmp-twsi";
433 interrupt-parent = <&intcmux17>;
437 #address-cells = <1>;
438 #size-cells = <0>;
443 compatible = "mrvl,mmp-rtc";
446 interrupt-names = "rtc 1Hz", "rtc alarm";
447 interrupt-parent = <&intcmux5>;
454 compatible = "marvell,mmp2-ssp";
458 #address-cells = <1>;
459 #size-cells = <0>;
464 compatible = "marvell,mmp2-ssp";
468 #address-cells = <1>;
469 #size-cells = <0>;
474 compatible = "marvell,mmp2-ssp";
478 #address-cells = <1>;
479 #size-cells = <0>;
484 compatible = "marvell,mmp2-ssp";
488 #address-cells = <1>;
489 #size-cells = <0>;
495 compatible = "mmio-sram";
498 #address-cells = <1>;
499 #size-cells = <1>;
504 compatible = "marvell,mmp2-clock";
508 reg-names = "mpmu", "apmu", "apbc";
509 #clock-cells = <1>;
510 #reset-cells = <1>;
511 #power-domain-cells = <1>;