Lines Matching +full:0 +full:x1550000
74 #size-cells = <0>;
79 reg = <0xf00>;
80 clocks = <&clockgen 1 0>;
87 reg = <0xf01>;
88 clocks = <&clockgen 1 0>;
95 reg = <0x0 0x0 0x0 0x0>;
100 #clock-cells = <0>;
123 offset = <0xb0>;
124 mask = <0x02>;
137 reg = <0x0 0x1080000 0x0 0x1000>;
146 reg = <0x0 0x1401000 0x0 0x1000>,
147 <0x0 0x1402000 0x0 0x2000>,
148 <0x0 0x1404000 0x0 0x2000>,
149 <0x0 0x1406000 0x0 0x2000>;
156 reg = <0x0 0x1570e00 0x0 0x8>;
163 reg = <0x0 0x1570e08 0x0 0x8>;
170 reg = <0x0 0x1530000 0x0 0x10000>;
176 reg = <0x0 0x1ee0000 0x0 0x1000>;
183 #size-cells = <0>;
184 reg = <0x0 0x1550000 0x0 0x10000>,
185 <0x0 0x40000000 0x0 0x20000000>;
195 reg = <0x0 0x1560000 0x0 0x10000>;
197 clock-frequency = <0>;
207 reg = <0x0 0x3200000 0x0 0x10000>,
208 <0x0 0x20220520 0x0 0x4>;
218 reg = <0x0 0x1570000 0x0 0x10000>;
222 ranges = <0x0 0x0 0x1570000 0x10000>;
227 #address-cells = <0>;
229 reg = <0x1ac 4>;
231 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
232 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
233 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
234 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
235 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
236 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-map-mask = <0xffffffff 0x0>;
242 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
246 reg = <0x0 0x1700000 0x0 0x100000>;
247 ranges = <0x0 0x0 0x1700000 0x100000>;
252 compatible = "fsl,sec-v5.0-job-ring",
253 "fsl,sec-v4.0-job-ring";
254 reg = <0x10000 0x10000>;
259 compatible = "fsl,sec-v5.0-job-ring",
260 "fsl,sec-v4.0-job-ring";
261 reg = <0x20000 0x10000>;
266 compatible = "fsl,sec-v5.0-job-ring",
267 "fsl,sec-v4.0-job-ring";
268 reg = <0x30000 0x10000>;
273 compatible = "fsl,sec-v5.0-job-ring",
274 "fsl,sec-v4.0-job-ring";
275 reg = <0x40000 0x10000>;
283 reg = <0x0 0x1ee1000 0x0 0x1000>;
290 reg = <0x0 0x1f00000 0x0 0x10000>;
292 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
293 fsl,tmu-calibration = <0x00000000 0x00000020
294 0x00000001 0x00000024
295 0x00000002 0x0000002a
296 0x00000003 0x00000032
297 0x00000004 0x00000038
298 0x00000005 0x0000003e
299 0x00000006 0x00000043
300 0x00000007 0x0000004a
301 0x00000008 0x00000050
302 0x00000009 0x00000059
303 0x0000000a 0x0000005f
304 0x0000000b 0x00000066
306 0x00010000 0x00000023
307 0x00010001 0x0000002b
308 0x00010002 0x00000033
309 0x00010003 0x0000003a
310 0x00010004 0x00000042
311 0x00010005 0x0000004a
312 0x00010006 0x00000054
313 0x00010007 0x0000005c
314 0x00010008 0x00000065
315 0x00010009 0x0000006f
317 0x00020000 0x00000029
318 0x00020001 0x00000033
319 0x00020002 0x0000003d
320 0x00020003 0x00000048
321 0x00020004 0x00000054
322 0x00020005 0x00000060
323 0x00020006 0x0000006c
325 0x00030000 0x00000025
326 0x00030001 0x00000033
327 0x00030002 0x00000043
328 0x00030003 0x00000055>;
337 thermal-sensors = <&tmu 0>;
366 compatible = "fsl,ls1021a-v1.0-dspi";
368 #size-cells = <0>;
369 reg = <0x0 0x2100000 0x0 0x10000>;
379 compatible = "fsl,ls1021a-v1.0-dspi";
381 #size-cells = <0>;
382 reg = <0x0 0x2110000 0x0 0x10000>;
394 #size-cells = <0>;
395 reg = <0x0 0x2180000 0x0 0x10000>;
407 #size-cells = <0>;
408 reg = <0x0 0x2190000 0x0 0x10000>;
420 #size-cells = <0>;
421 reg = <0x0 0x21a0000 0x0 0x10000>;
432 reg = <0x0 0x21c0500 0x0 0x100>;
434 clock-frequency = <0>;
441 reg = <0x0 0x21c0600 0x0 0x100>;
443 clock-frequency = <0>;
450 reg = <0x0 0x21d0500 0x0 0x100>;
452 clock-frequency = <0>;
459 reg = <0x0 0x21d0600 0x0 0x100>;
461 clock-frequency = <0>;
468 reg = <0x0 0x29d0000 0x0 0x10000>;
475 reg = <0x0 0x29e0000 0x0 0x10000>;
482 reg = <0x0 0x29f0000 0x0 0x10000>;
489 reg = <0x0 0x2a00000 0x0 0x10000>;
496 reg = <0x0 0x2300000 0x0 0x10000>;
506 reg = <0x0 0x2310000 0x0 0x10000>;
516 reg = <0x0 0x2320000 0x0 0x10000>;
526 reg = <0x0 0x2330000 0x0 0x10000>;
536 reg = <0x0 0x2950000 0x0 0x1000>;
545 reg = <0x0 0x2960000 0x0 0x1000>;
554 reg = <0x0 0x2970000 0x0 0x1000>;
563 reg = <0x0 0x2980000 0x0 0x1000>;
572 reg = <0x0 0x2990000 0x0 0x1000>;
581 reg = <0x0 0x29a0000 0x0 0x1000>;
591 reg = <0x0 0x29d0000 0x0 0x10000>;
603 reg = <0x0 0x29e0000 0x0 0x10000>;
615 reg = <0x0 0x29f0000 0x0 0x10000>;
627 reg = <0x0 0x2a00000 0x0 0x10000>;
639 reg = <0x0 0x2a10000 0x0 0x10000>;
651 reg = <0x0 0x2a20000 0x0 0x10000>;
663 reg = <0x0 0x2a30000 0x0 0x10000>;
675 reg = <0x0 0x2a40000 0x0 0x10000>;
686 reg = <0x0 0x2ad0000 0x0 0x10000>;
694 #sound-dai-cells = <0>;
696 reg = <0x0 0x2b50000 0x0 0x10000>;
708 #sound-dai-cells = <0>;
710 reg = <0x0 0x2b60000 0x0 0x10000>;
724 reg = <0x0 0x2c00000 0x0 0x10000>,
725 <0x0 0x2c10000 0x0 0x10000>,
726 <0x0 0x2c20000 0x0 0x10000>;
739 reg = <0x0 0x2ce0000 0x0 0x10000>;
741 clocks = <&clockgen 4 0>,
742 <&clockgen 4 0>;
752 #size-cells = <0>;
753 reg = <0x0 0x2d24000 0x0 0x4000>,
754 <0x0 0x2d10030 0x0 0x4>;
761 #size-cells = <0>;
762 reg = <0x0 0x2d64000 0x0 0x4000>,
763 <0x0 0x2d50030 0x0 0x4>;
768 reg = <0x0 0x2d10e00 0x0 0xb0>;
772 fsl,tmr-add = <0xaaaaaaab>;
793 reg = <0x0 0x2d10000 0x0 0x1000>;
802 reg = <0x0 0x2d14000 0x0 0x1000>;
822 reg = <0x0 0x2d50000 0x0 0x1000>;
831 reg = <0x0 0x2d54000 0x0 0x1000>;
851 reg = <0x0 0x2d90000 0x0 0x1000>;
860 reg = <0x0 0x2d94000 0x0 0x1000>;
869 reg = <0x0 0x8600000 0x0 0x1000>;
877 reg = <0x0 0x3100000 0x0 0x10000>;
880 snps,quirk-frame-length-adjustment = <0x20>;
887 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
888 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
891 fsl,pcie-scfg = <&scfg 0>;
896 bus-range = <0x0 0xff>;
897 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
898 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
901 interrupt-map-mask = <0 0 0 7>;
902 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
903 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
904 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
905 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
911 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
912 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
920 bus-range = <0x0 0xff>;
921 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
922 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
925 interrupt-map-mask = <0 0 0 7>;
926 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
927 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
928 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
929 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
935 reg = <0x0 0x2a70000 0x0 0x1000>;
944 reg = <0x0 0x2a80000 0x0 0x1000>;
953 reg = <0x0 0x2a90000 0x0 0x1000>;
962 reg = <0x0 0x2aa0000 0x0 0x1000>;
971 reg = <0x0 0x10000000 0x0 0x10000>;
974 ranges = <0x0 0x0 0x10000000 0x10000>;
979 reg = <0x0 0x10010000 0x0 0x10000>;
982 ranges = <0x0 0x0 0x10010000 0x10000>;
987 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
988 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
989 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
997 block-offset = <0x1000>;
1006 reg = <0x0 0x1ee2140 0x0 0x8>;
1012 reg = <0x0 0x29d0000 0x0 0x10000>;
1014 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;