Lines Matching +full:rx +full:- +full:int +full:- +full:gpios
1 // SPDX-License-Identifier: ISC
7 /dts-v1/;
9 #include "intel-ixp42x.dtsi"
10 #include <dt-bindings/input/input.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
25 stdout-path = "uart0:115200n8";
33 compatible = "gpio-leds";
34 led-user {
36 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
37 default-state = "on";
38 linux,default-trigger = "heartbeat";
43 compatible = "i2c-gpio";
44 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
46 #address-cells = <1>;
47 #size-cells = <0>;
62 read-only;
69 compatible = "intel,ixp4xx-flash", "cfi-flash";
70 bank-width = <2>;
72 intel,ixp4xx-eb-write-enable = <1>;
77 compatible = "redboot-fis";
79 fis-index-block = <0x7f>;
83 compatible = "intel,ixp4xx-compact-flash";
87 * depending on selected PIO mode (0-4).
89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
94 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
95 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
96 intel,ixp4xx-eb-mux-address-and-data = <0>;
97 intel,ixp4xx-eb-ahb-split-transfers = <0>;
98 intel,ixp4xx-eb-write-enable = <1>;
99 intel,ixp4xx-eb-byte-access = <1>;
102 interrupt-parent = <&gpio0>;
118 interrupt-map =
120 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
121 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
122 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
123 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
125 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
126 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
127 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
128 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
130 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
131 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
132 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
133 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
135 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
136 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
137 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
138 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
144 queue-rx = <&qmgr 3>;
145 queue-txready = <&qmgr 20>;
146 phy-mode = "rgmii";
147 phy-handle = <&phy0>;
150 #address-cells = <1>;
151 #size-cells = <0>;
153 phy0: ethernet-phy@0 {
157 phy1: ethernet-phy@1 {
166 queue-rx = <&qmgr 4>;
167 queue-txready = <&qmgr 21>;
168 phy-mode = "rgmii";
169 phy-handle = <&phy1>;